Commit 46a51abb authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'socfpga_dts_for_v4.3' of... 

Merge tag 'socfpga_dts_for_v4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into next/dt

SoCFPGA DTS updates for v4.3
- Update clocking for DTS nodes
- Add DTS board file for Terasic DE0 Atlas board
- Use stdout-patch for chosen node
- Enable prefetch-data and prefetch-instr

* tag 'socfpga_dts_for_v4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux

:
  ARM: socfpga: dts: add osc1 as a possible parent for dbg_base_clk
  ARM: socfpga: dts: add missing clock gates to socfpga.dtsi
  ARM: socfpga: dts: Fix gpio dts entry for the correct clock
  ARM: socfpga: dts: Correct the parent clock for l3_sp_clk and dbg_clk
  ARM: dts: socfpga: Add support of Terasic DE0 Atlas board
  ARM: dts: socfpga: use stdout-path for chosen node
  ARM: dts: socfpga: enable the data and instruction prefetch for the l2 cache

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 55e3cfc5 2e4c7588

arch/arm/boot/dts/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -536,6 +536,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \ 
	socfpga_arria5_socdk.dtb \

	socfpga_arria10_socdk_sdmmc.dtb \

	socfpga_cyclone5_socdk.dtb \

	socfpga_cyclone5_de0_sockit.dtb \

	socfpga_cyclone5_sockit.dtb \

	socfpga_cyclone5_socrates.dtb \

	socfpga_vt.dtb

arch/arm/boot/dts/socfpga.dtsi

+38 −7
Original line number Diff line number Diff line
@@ -164,7 +164,7 @@ 
						dbg_base_clk: dbg_base_clk {

							#clock-cells = <0>;

							compatible = "altr,socfpga-perip-clk";

							clocks = <&main_pll>;

							clocks = <&main_pll>, <&osc1>;

							div-reg = <0xe8 0 9>;

							reg = <0x50>;

						};
@@ -318,7 +318,7 @@ 
					l3_sp_clk: l3_sp_clk {

						#clock-cells = <0>;

						compatible = "altr,socfpga-gate-clk";

						clocks = <&mainclk>;

						clocks = <&l3_mp_clk>;

						div-reg = <0x64 2 2>;

					};
@@ -349,7 +349,7 @@ 
					dbg_clk: dbg_clk {

						#clock-cells = <0>;

						compatible = "altr,socfpga-gate-clk";

						clocks = <&dbg_base_clk>;

						clocks = <&dbg_at_clk>;

						div-reg = <0x68 2 2>;

						clk-gate = <0x60 5>;

					};
@@ -481,6 +481,35 @@ 
						clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;

						clk-gate = <0xa0 11>;

					};



					ddr_dqs_clk_gate: ddr_dqs_clk_gate {

						#clock-cells = <0>;

						compatible = "altr,socfpga-gate-clk";

						clocks = <&ddr_dqs_clk>;

						clk-gate = <0xd8 0>;

					};



					ddr_2x_dqs_clk_gate: ddr_2x_dqs_clk_gate {

						#clock-cells = <0>;

						compatible = "altr,socfpga-gate-clk";

						clocks = <&ddr_2x_dqs_clk>;

						clk-gate = <0xd8 1>;

					};



					ddr_dq_clk_gate: ddr_dq_clk_gate {

						#clock-cells = <0>;

						compatible = "altr,socfpga-gate-clk";

						clocks = <&ddr_dq_clk>;

						clk-gate = <0xd8 2>;

					};



					h2f_user2_clk: h2f_user2_clk {

						#clock-cells = <0>;

						compatible = "altr,socfpga-gate-clk";

						clocks = <&h2f_usr2_clk>;

						clk-gate = <0xd8 3>;

					};



				};

		};
@@ -565,7 +594,7 @@ 
			#size-cells = <0>;

			compatible = "snps,dw-apb-gpio";

			reg = <0xff708000 0x1000>;

			clocks = <&per_base_clk>;

			clocks = <&l4_mp_clk>;

			status = "disabled";



			porta: gpio-controller@0 {
@@ -585,7 +614,7 @@ 
			#size-cells = <0>;

			compatible = "snps,dw-apb-gpio";

			reg = <0xff709000 0x1000>;

			clocks = <&per_base_clk>;

			clocks = <&l4_mp_clk>;

			status = "disabled";



			portb: gpio-controller@0 {
@@ -605,7 +634,7 @@ 
			#size-cells = <0>;

			compatible = "snps,dw-apb-gpio";

			reg = <0xff70a000 0x1000>;

			clocks = <&per_base_clk>;

			clocks = <&l4_mp_clk>;

			status = "disabled";



			portc: gpio-controller@0 {
@@ -639,6 +668,8 @@ 
			cache-level = <2>;

			arm,tag-latency = <1 1 1>;

			arm,data-latency = <2 1 1>;

			prefetch-data = <1>;

			prefetch-instr = <1>;

		};



		mmc: dwmmc0@ff704000 {

arch/arm/boot/dts/socfpga_arria10.dtsi

+5 −0
Original line number Diff line number Diff line
@@ -21,6 +21,11 @@ 
	#address-cells = <1>;

	#size-cells = <1>;



	aliases {

		serial0 = &uart0;

		serial1 = &uart1;

	};



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;

arch/arm/boot/dts/socfpga_arria10_socdk.dtsi

+2 −1
Original line number Diff line number Diff line
@@ -21,7 +21,8 @@ 
	compatible = "altr,socfpga-arria10", "altr,socfpga";



	chosen {

		bootargs = "console=ttyS0,115200 rootwait";

		bootargs = "earlyprintk";

		stdout-path = "serial1:115200n8";

	};



	memory {

arch/arm/boot/dts/socfpga_arria5_socdk.dts

+2 −1
Original line number Diff line number Diff line
@@ -22,7 +22,8 @@ 
	compatible = "altr,socfpga-arria5", "altr,socfpga";



	chosen {

		bootargs = "console=ttyS0,115200";

		bootargs = "earlyprintk";

		stdout-path = "serial0:115200n8";

	};



	memory {

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