Commit 467e8a51 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-2018-12-04' of git://anongit.freedesktop.org/drm/drm-intel into drm-next 



Final drm/i915 changes for v4.21:
- ICL DSI video mode enabling (Madhav, Vandita, Jani, Imre)
- eDP sink count fix (José)
- PSR fixes (José)
- DRM DP helper and i915 DSC enabling (Manasi, Gaurav, Anusha)
- DP FEC enabling (Anusha)
- SKL+ watermark/ddb programming improvements (Ville)
- Pixel format fixes (Ville)
- Selftest updates (Chris, Tvrtko)
- GT and engine workaround improvements (Tvrtko)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/87va496uoe.fsf@intel.com
parents 818182dd 4377d4e0

Documentation/gpu/drm-kms-helpers.rst

+12 −0
Original line number Original line Diff line number Diff line
@@ -232,6 +232,18 @@ MIPI DSI Helper Functions Reference 
.. kernel-doc:: drivers/gpu/drm/drm_mipi_dsi.c

.. kernel-doc:: drivers/gpu/drm/drm_mipi_dsi.c

   :export:

   :export:





Display Stream Compression Helper Functions Reference

=====================================================



.. kernel-doc:: drivers/gpu/drm/drm_dsc.c

   :doc: dsc helpers



.. kernel-doc:: include/drm/drm_dsc.h

   :internal:



.. kernel-doc:: drivers/gpu/drm/drm_dsc.c

   :export:



Output Probing Helper Functions Reference

Output Probing Helper Functions Reference

=========================================

=========================================

drivers/gpu/drm/Makefile

+1 −1
Original line number Original line Diff line number Diff line
@@ -32,7 +32,7 @@ drm-$(CONFIG_AGP) += drm_agpsupport.o 
drm-$(CONFIG_DEBUG_FS) += drm_debugfs.o drm_debugfs_crc.o

drm-$(CONFIG_DEBUG_FS) += drm_debugfs.o drm_debugfs_crc.o

drm-$(CONFIG_DRM_LOAD_EDID_FIRMWARE) += drm_edid_load.o

drm-$(CONFIG_DRM_LOAD_EDID_FIRMWARE) += drm_edid_load.o





drm_kms_helper-y := drm_crtc_helper.o drm_dp_helper.o drm_probe_helper.o \

drm_kms_helper-y := drm_crtc_helper.o drm_dp_helper.o drm_dsc.o drm_probe_helper.o \

		drm_plane_helper.o drm_dp_mst_topology.o drm_atomic_helper.o \

		drm_plane_helper.o drm_dp_mst_topology.o drm_atomic_helper.o \

		drm_kms_helper_common.o drm_dp_dual_mode_helper.o \

		drm_kms_helper_common.o drm_dp_dual_mode_helper.o \

		drm_simple_kms_helper.o drm_modeset_helper.o \

		drm_simple_kms_helper.o drm_modeset_helper.o \

drivers/gpu/drm/drm_dp_helper.c

+8 −6
Original line number Original line Diff line number Diff line
@@ -1428,17 +1428,19 @@ u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) 
}

}

EXPORT_SYMBOL(drm_dp_dsc_sink_line_buf_depth);

EXPORT_SYMBOL(drm_dp_dsc_sink_line_buf_depth);





u8 drm_dp_dsc_sink_max_color_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])

int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],

					 u8 dsc_bpc[3])

{

{

	int num_bpc = 0;

	u8 color_depth = dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP - DP_DSC_SUPPORT];

	u8 color_depth = dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP - DP_DSC_SUPPORT];





	if (color_depth & DP_DSC_12_BPC)

	if (color_depth & DP_DSC_12_BPC)

		return 12;

		dsc_bpc[num_bpc++] = 12;

	if (color_depth & DP_DSC_10_BPC)

	if (color_depth & DP_DSC_10_BPC)

		return 10;

		dsc_bpc[num_bpc++] = 10;

	if (color_depth & DP_DSC_8_BPC)

	if (color_depth & DP_DSC_8_BPC)

		return 8;

		dsc_bpc[num_bpc++] = 8;





	return 0;

	return num_bpc;

}

}

EXPORT_SYMBOL(drm_dp_dsc_sink_max_color_depth);
 
EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);

drivers/gpu/drm/drm_dsc.c

0 → 100644
+228 −0
Original line number Original line Diff line number Diff line 
// SPDX-License-Identifier: MIT

/*

 * Copyright © 2018 Intel Corp

 *

 * Author:

 * Manasi Navare <manasi.d.navare@intel.com>

 */



#include <linux/kernel.h>

#include <linux/module.h>

#include <linux/init.h>

#include <linux/errno.h>

#include <linux/byteorder/generic.h>

#include <drm/drm_dp_helper.h>

#include <drm/drm_dsc.h>



/**

 * DOC: dsc helpers

 *

 * These functions contain some common logic and helpers to deal with VESA

 * Display Stream Compression standard required for DSC on Display Port/eDP or

 * MIPI display interfaces.

 */



/**

 * drm_dsc_dp_pps_header_init() - Initializes the PPS Header

 * for DisplayPort as per the DP 1.4 spec.

 * @pps_sdp: Secondary data packet for DSC Picture Parameter Set

 */

void drm_dsc_dp_pps_header_init(struct drm_dsc_pps_infoframe *pps_sdp)

{

	memset(&pps_sdp->pps_header, 0, sizeof(pps_sdp->pps_header));



	pps_sdp->pps_header.HB1 = DP_SDP_PPS;

	pps_sdp->pps_header.HB2 = DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1;

}

EXPORT_SYMBOL(drm_dsc_dp_pps_header_init);



/**

 * drm_dsc_pps_infoframe_pack() - Populates the DSC PPS infoframe

 * using the DSC configuration parameters in the order expected

 * by the DSC Display Sink device. For the DSC, the sink device

 * expects the PPS payload in the big endian format for the fields

 * that span more than 1 byte.

 *

 * @pps_sdp:

 * Secondary data packet for DSC Picture Parameter Set

 * @dsc_cfg:

 * DSC Configuration data filled by driver

 */

void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp,

				const struct drm_dsc_config *dsc_cfg)

{

	int i;



	/* Protect against someone accidently changing struct size */

	BUILD_BUG_ON(sizeof(pps_sdp->pps_payload) !=

		     DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 + 1);



	memset(&pps_sdp->pps_payload, 0, sizeof(pps_sdp->pps_payload));



	/* PPS 0 */

	pps_sdp->pps_payload.dsc_version =

		dsc_cfg->dsc_version_minor |

		dsc_cfg->dsc_version_major << DSC_PPS_VERSION_MAJOR_SHIFT;



	/* PPS 1, 2 is 0 */



	/* PPS 3 */

	pps_sdp->pps_payload.pps_3 =

		dsc_cfg->line_buf_depth |

		dsc_cfg->bits_per_component << DSC_PPS_BPC_SHIFT;



	/* PPS 4 */

	pps_sdp->pps_payload.pps_4 =

		((dsc_cfg->bits_per_pixel & DSC_PPS_BPP_HIGH_MASK) >>

		 DSC_PPS_MSB_SHIFT) |

		dsc_cfg->vbr_enable << DSC_PPS_VBR_EN_SHIFT |

		dsc_cfg->enable422 << DSC_PPS_SIMPLE422_SHIFT |

		dsc_cfg->convert_rgb << DSC_PPS_CONVERT_RGB_SHIFT |

		dsc_cfg->block_pred_enable << DSC_PPS_BLOCK_PRED_EN_SHIFT;



	/* PPS 5 */

	pps_sdp->pps_payload.bits_per_pixel_low =

		(dsc_cfg->bits_per_pixel & DSC_PPS_LSB_MASK);



	/*

	 * The DSC panel expects the PPS packet to have big endian format

	 * for data spanning 2 bytes. Use a macro cpu_to_be16() to convert

	 * to big endian format. If format is little endian, it will swap

	 * bytes to convert to Big endian else keep it unchanged.

	 */



	/* PPS 6, 7 */

	pps_sdp->pps_payload.pic_height = cpu_to_be16(dsc_cfg->pic_height);



	/* PPS 8, 9 */

	pps_sdp->pps_payload.pic_width = cpu_to_be16(dsc_cfg->pic_width);



	/* PPS 10, 11 */

	pps_sdp->pps_payload.slice_height = cpu_to_be16(dsc_cfg->slice_height);



	/* PPS 12, 13 */

	pps_sdp->pps_payload.slice_width = cpu_to_be16(dsc_cfg->slice_width);



	/* PPS 14, 15 */

	pps_sdp->pps_payload.chunk_size = cpu_to_be16(dsc_cfg->slice_chunk_size);



	/* PPS 16 */

	pps_sdp->pps_payload.initial_xmit_delay_high =

		((dsc_cfg->initial_xmit_delay &

		  DSC_PPS_INIT_XMIT_DELAY_HIGH_MASK) >>

		 DSC_PPS_MSB_SHIFT);



	/* PPS 17 */

	pps_sdp->pps_payload.initial_xmit_delay_low =

		(dsc_cfg->initial_xmit_delay & DSC_PPS_LSB_MASK);



	/* PPS 18, 19 */

	pps_sdp->pps_payload.initial_dec_delay =

		cpu_to_be16(dsc_cfg->initial_dec_delay);



	/* PPS 20 is 0 */



	/* PPS 21 */

	pps_sdp->pps_payload.initial_scale_value =

		dsc_cfg->initial_scale_value;



	/* PPS 22, 23 */

	pps_sdp->pps_payload.scale_increment_interval =

		cpu_to_be16(dsc_cfg->scale_increment_interval);



	/* PPS 24 */

	pps_sdp->pps_payload.scale_decrement_interval_high =

		((dsc_cfg->scale_decrement_interval &

		  DSC_PPS_SCALE_DEC_INT_HIGH_MASK) >>

		 DSC_PPS_MSB_SHIFT);



	/* PPS 25 */

	pps_sdp->pps_payload.scale_decrement_interval_low =

		(dsc_cfg->scale_decrement_interval & DSC_PPS_LSB_MASK);



	/* PPS 26[7:0], PPS 27[7:5] RESERVED */



	/* PPS 27 */

	pps_sdp->pps_payload.first_line_bpg_offset =

		dsc_cfg->first_line_bpg_offset;



	/* PPS 28, 29 */

	pps_sdp->pps_payload.nfl_bpg_offset =

		cpu_to_be16(dsc_cfg->nfl_bpg_offset);



	/* PPS 30, 31 */

	pps_sdp->pps_payload.slice_bpg_offset =

		cpu_to_be16(dsc_cfg->slice_bpg_offset);



	/* PPS 32, 33 */

	pps_sdp->pps_payload.initial_offset =

		cpu_to_be16(dsc_cfg->initial_offset);



	/* PPS 34, 35 */

	pps_sdp->pps_payload.final_offset = cpu_to_be16(dsc_cfg->final_offset);



	/* PPS 36 */

	pps_sdp->pps_payload.flatness_min_qp = dsc_cfg->flatness_min_qp;



	/* PPS 37 */

	pps_sdp->pps_payload.flatness_max_qp = dsc_cfg->flatness_max_qp;



	/* PPS 38, 39 */

	pps_sdp->pps_payload.rc_model_size =

		cpu_to_be16(DSC_RC_MODEL_SIZE_CONST);



	/* PPS 40 */

	pps_sdp->pps_payload.rc_edge_factor = DSC_RC_EDGE_FACTOR_CONST;



	/* PPS 41 */

	pps_sdp->pps_payload.rc_quant_incr_limit0 =

		dsc_cfg->rc_quant_incr_limit0;



	/* PPS 42 */

	pps_sdp->pps_payload.rc_quant_incr_limit1 =

		dsc_cfg->rc_quant_incr_limit1;



	/* PPS 43 */

	pps_sdp->pps_payload.rc_tgt_offset = DSC_RC_TGT_OFFSET_LO_CONST |

		DSC_RC_TGT_OFFSET_HI_CONST << DSC_PPS_RC_TGT_OFFSET_HI_SHIFT;



	/* PPS 44 - 57 */

	for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++)

		pps_sdp->pps_payload.rc_buf_thresh[i] =

			dsc_cfg->rc_buf_thresh[i];



	/* PPS 58 - 87 */

	/*

	 * For DSC sink programming the RC Range parameter fields

	 * are as follows: Min_qp[15:11], max_qp[10:6], offset[5:0]

	 */

	for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {

		pps_sdp->pps_payload.rc_range_parameters[i] =

			((dsc_cfg->rc_range_params[i].range_min_qp <<

			  DSC_PPS_RC_RANGE_MINQP_SHIFT) |

			 (dsc_cfg->rc_range_params[i].range_max_qp <<

			  DSC_PPS_RC_RANGE_MAXQP_SHIFT) |

			 (dsc_cfg->rc_range_params[i].range_bpg_offset));

		pps_sdp->pps_payload.rc_range_parameters[i] =

			cpu_to_be16(pps_sdp->pps_payload.rc_range_parameters[i]);

	}



	/* PPS 88 */

	pps_sdp->pps_payload.native_422_420 = dsc_cfg->native_422 |

		dsc_cfg->native_420 << DSC_PPS_NATIVE_420_SHIFT;



	/* PPS 89 */

	pps_sdp->pps_payload.second_line_bpg_offset =

		dsc_cfg->second_line_bpg_offset;



	/* PPS 90, 91 */

	pps_sdp->pps_payload.nsl_bpg_offset =

		cpu_to_be16(dsc_cfg->nsl_bpg_offset);



	/* PPS 92, 93 */

	pps_sdp->pps_payload.second_line_offset_adj =

		cpu_to_be16(dsc_cfg->second_line_offset_adj);



	/* PPS 94 - 127 are O */

}

EXPORT_SYMBOL(drm_dsc_pps_infoframe_pack);

drivers/gpu/drm/i915/Makefile

+5 −2
Original line number Original line Diff line number Diff line
@@ -157,14 +157,17 @@ i915-y += dvo_ch7017.o \ 
	  intel_sdvo.o \

	  intel_sdvo.o \

	  intel_tv.o \

	  intel_tv.o \

	  vlv_dsi.o \

	  vlv_dsi.o \

	  vlv_dsi_pll.o

	  vlv_dsi_pll.o \

	  intel_vdsc.o





# Post-mortem debug and GPU hang state capture

# Post-mortem debug and GPU hang state capture

i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o

i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o

i915-$(CONFIG_DRM_I915_SELFTEST) += \

i915-$(CONFIG_DRM_I915_SELFTEST) += \

	selftests/i915_random.o \

	selftests/i915_random.o \

	selftests/i915_selftest.o \

	selftests/i915_selftest.o \

	selftests/igt_flush_test.o

	selftests/igt_flush_test.o \

	selftests/igt_reset.o \

	selftests/igt_spinner.o





# virtual gpu code

# virtual gpu code

i915-y += i915_vgpu.o

i915-y += i915_vgpu.o

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