irqchip/sifive-plic: Support irq domain hierarchy (466008f9) · Commits · 戴 / test

drivers/irqchip/Kconfig

+1 −0

Original line number	Diff line number	Diff line
		@@ -490,6 +490,7 @@ config TI_SCI_INTA_IRQCHIP
		config SIFIVE_PLIC
		bool "SiFive Platform-Level Interrupt Controller"
		depends on RISCV
		select IRQ_DOMAIN_HIERARCHY
		help
		This enables support for the PLIC chip found in SiFive (and
		potentially other) RISC-V systems. The PLIC controls devices

+26 −4

Original line number	Diff line number	Diff line
		@@ -154,15 +154,37 @@ static struct irq_chip plic_chip = {
		static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq,
		irq_hw_number_t hwirq)
		{
		irq_set_chip_and_handler(irq, &plic_chip, handle_fasteoi_irq);
		irq_set_chip_data(irq, NULL);
		irq_domain_set_info(d, irq, hwirq, &plic_chip, d->host_data,
		handle_fasteoi_irq, NULL, NULL);
		irq_set_noprobe(irq);
		return 0;
		}

		static int plic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
		unsigned int nr_irqs, void *arg)
		{
		int i, ret;
		irq_hw_number_t hwirq;
		unsigned int type;
		struct irq_fwspec *fwspec = arg;

		ret = irq_domain_translate_onecell(domain, fwspec, &hwirq, &type);
		if (ret)
		return ret;

		for (i = 0; i < nr_irqs; i++) {
		ret = plic_irqdomain_map(domain, virq + i, hwirq + i);
		if (ret)
		return ret;
		}

		return 0;
		}

		static const struct irq_domain_ops plic_irqdomain_ops = {
		.map = plic_irqdomain_map,
		.xlate = irq_domain_xlate_onecell,
		.translate = irq_domain_translate_onecell,
		.alloc = plic_irq_domain_alloc,
		.free = irq_domain_free_irqs_top,
		};

		static struct irq_domain *plic_irqdomain;