Commit 46561217 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'reset-for-5.0-rc2' of git://git.pengutronix.de/git/pza/linux into fixes 

Late reset controller changes for v5.0

This adds missing deassert functionality to the ARC HSDK reset driver,
fixes some indentation and grammar issues in the kernel docs, adds a
helper to count the number of resets on a device for the non-DT case
as well, adds an early reset driver for SoCFPGA and simple reset driver
support for Stratix10, and generalizes the uniphier USB3 glue layer
reset to also cover AHCI.

* tag 'reset-for-5.0-rc2' of git://git.pengutronix.de/git/pza/linux

:
  reset: uniphier-glue: Add AHCI reset control support in glue layer
  dt-bindings: reset: uniphier: Add AHCI core reset description
  reset: uniphier-usb3: Rename to reset-uniphier-glue
  dt-bindings: reset: uniphier: Replace the expression of USB3 with generic peripherals
  ARM: socfpga: dts: document "altr,stratix10-rst-mgr" binding
  reset: socfpga: add an early reset driver for SoCFPGA
  reset: fix null pointer dereference on dev by dev_name
  reset: Add reset_control_get_count()
  reset: Improve reset controller kernel docs
  ARC: HSDK: improve reset driver

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 56acb3ef d0c2d210

Documentation/devicetree/bindings/reset/socfpga-reset.txt

+2 −1
Original line number Diff line number Diff line 
Altera SOCFPGA Reset Manager



Required properties:

- compatible : "altr,rst-mgr"

- compatible : "altr,rst-mgr" for (Cyclone5/Arria5/Arria10)

	       "altr,stratix10-rst-mgr","altr,rst-mgr" for Stratix10 ARM64 SoC

- reg : Should contain 1 register ranges(address and length)

- altr,modrst-offset : Should contain the offset of the first modrst register.

- #reset-cells: 1

Documentation/devicetree/bindings/reset/uniphier-reset.txt

+14 −11
Original line number Diff line number Diff line
@@ -120,27 +120,30 @@ Example: 
	};





USB3 core reset

---------------

Peripheral core reset in glue layer

-----------------------------------



USB3 core reset belongs to USB3 glue layer. Before using the core reset,

it is necessary to control the clocks and resets to enable this layer.

These clocks and resets should be described in each property.

Some peripheral core reset belongs to its own glue layer. Before using

this core reset, it is necessary to control the clocks and resets to enable

this layer. These clocks and resets should be described in each property.



Required properties:

- compatible: Should be

    "socionext,uniphier-pro4-usb3-reset" - for Pro4 SoC

    "socionext,uniphier-pxs2-usb3-reset" - for PXs2 SoC

    "socionext,uniphier-ld20-usb3-reset" - for LD20 SoC

    "socionext,uniphier-pxs3-usb3-reset" - for PXs3 SoC

    "socionext,uniphier-pro4-usb3-reset" - for Pro4 SoC USB3

    "socionext,uniphier-pxs2-usb3-reset" - for PXs2 SoC USB3

    "socionext,uniphier-ld20-usb3-reset" - for LD20 SoC USB3

    "socionext,uniphier-pxs3-usb3-reset" - for PXs3 SoC USB3

    "socionext,uniphier-pro4-ahci-reset" - for Pro4 SoC AHCI

    "socionext,uniphier-pxs2-ahci-reset" - for PXs2 SoC AHCI

    "socionext,uniphier-pxs3-ahci-reset" - for PXs3 SoC AHCI

- #reset-cells: Should be 1.

- reg: Specifies offset and length of the register set for the device.

- clocks: A list of phandles to the clock gate for USB3 glue layer.

- clocks: A list of phandles to the clock gate for the glue layer.

	According to the clock-names, appropriate clocks are required.

- clock-names: Should contain

    "gio", "link" - for Pro4 SoC

    "link"        - for others

- resets: A list of phandles to the reset control for USB3 glue layer.

- resets: A list of phandles to the reset control for the glue layer.

	According to the reset-names, appropriate resets are required.

- reset-names: Should contain

    "gio", "link" - for Pro4 SoC

arch/arm/mach-socfpga/socfpga.c

+4 −0
Original line number Diff line number Diff line
@@ -32,6 +32,8 @@ void __iomem *rst_manager_base_addr; 
void __iomem *sdr_ctl_base_addr;

unsigned long socfpga_cpu1start_addr;



extern void __init socfpga_reset_init(void);



static void __init socfpga_sysmgr_init(void)

{

	struct device_node *np;
@@ -64,6 +66,7 @@ static void __init socfpga_init_irq(void) 


	if (IS_ENABLED(CONFIG_EDAC_ALTERA_OCRAM))

		socfpga_init_ocram_ecc();

	socfpga_reset_init();

}



static void __init socfpga_arria10_init_irq(void)
@@ -74,6 +77,7 @@ static void __init socfpga_arria10_init_irq(void) 
		socfpga_init_arria10_l2_ecc();

	if (IS_ENABLED(CONFIG_EDAC_ALTERA_OCRAM))

		socfpga_init_arria10_ocram_ecc();

	socfpga_reset_init();

}



static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd)

drivers/reset/Kconfig

+14 −6
Original line number Diff line number Diff line
@@ -109,7 +109,7 @@ config RESET_QCOM_PDC 


config RESET_SIMPLE

	bool "Simple Reset Controller Driver" if COMPILE_TEST

	default ARCH_SOCFPGA || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARCH_ASPEED

	default ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARCH_ASPEED

	help

	  This enables a simple reset controller driver for reset lines that

	  that can be asserted and deasserted by toggling bits in a contiguous,
@@ -128,6 +128,14 @@ config RESET_STM32MP157 
	help

	  This enables the RCC reset controller driver for STM32 MPUs.



config RESET_SOCFPGA

	bool "SoCFPGA Reset Driver" if COMPILE_TEST && !ARCH_SOCFPGA

	default ARCH_SOCFPGA

	select RESET_SIMPLE

	help

	  This enables the reset driver for the SoCFPGA ARMv7 platforms. This

	  driver gets initialized early during platform init calls.



config RESET_SUNXI

	bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI

	default ARCH_SUNXI
@@ -163,15 +171,15 @@ config RESET_UNIPHIER 
	  Say Y if you want to control reset signals provided by System Control

	  block, Media I/O block, Peripheral Block.



config RESET_UNIPHIER_USB3

	tristate "USB3 reset driver for UniPhier SoCs"

config RESET_UNIPHIER_GLUE

	tristate "Reset driver in glue layer for UniPhier SoCs"

	depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF

	default ARCH_UNIPHIER

	select RESET_SIMPLE

	help

	  Support for the USB3 core reset on UniPhier SoCs.

	  Say Y if you want to control reset signals provided by

	  USB3 glue layer.

	  Support for peripheral core reset included in its own glue layer

	  on UniPhier SoCs. Say Y if you want to control reset signals

	  provided by the glue layer.



config RESET_ZYNQ

	bool "ZYNQ Reset Driver" if COMPILE_TEST

drivers/reset/Makefile

+2 −1
Original line number Diff line number Diff line
@@ -19,10 +19,11 @@ obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o 
obj-$(CONFIG_RESET_QCOM_PDC) += reset-qcom-pdc.o

obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o

obj-$(CONFIG_RESET_STM32MP157) += reset-stm32mp1.o

obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o

obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o

obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o

obj-$(CONFIG_RESET_TI_SYSCON) += reset-ti-syscon.o

obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o

obj-$(CONFIG_RESET_UNIPHIER_USB3) += reset-uniphier-usb3.o

obj-$(CONFIG_RESET_UNIPHIER_GLUE) += reset-uniphier-glue.o

obj-$(CONFIG_RESET_ZYNQ) += reset-zynq.o

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