Commit 4645e906 authored by Anshuman Gupta's avatar Anshuman Gupta Committed by Imre Deak
Browse files

drm/i915/tgl: Enable DC3CO state in "DC Off" power well 



Add target_dc_state and used by set_target_dc_state API
in order to enable DC3CO state with existing DC states.
target_dc_state will enable/disable the desired DC state in
DC_STATE_EN reg when "DC Off" power well gets disable/enable.

v2: commit log improvement.
v3: Used intel_wait_for_register to wait for DC3CO exit. [Imre]
    Used gen9_set_dc_state() to allow/disallow DC3CO. [Imre]
    Moved transcoder psr2 exit line enablement from tgl_allow_dc3co()
    to a appropriate place haswell_crtc_enable(). [Imre]
    Changed the DC3CO power well enabled call back logic as
    recommended in review comments. [Imre]
v4: Used wait_for_us() instead of intel_wait_for_reg(). [Imre (IRC)]
v5: using udelay() instead of waiting for DC3CO exit status.
v6: Fixed minor unwanted change.
v7: Removed DC3CO powerwell and POWER_DOMAIN_VIDEO.
v8: Uniform checks by using only target_dc_state instead of allowed_dc_mask
    in "DC off" power well callback. [Imre]
    Adding "DC off" power well id to older platforms. [Imre]
    Removed psr2_deep_sleep flag from tgl_set_target_dc_state. [Imre]
v9: Used switch case for target DC state in
    gen9_dc_off_power_well_disable(), checking DC3CO state against
    allowed DC mask, using WARN_ON() in
    tgl_set_target_dc_state(). [Imre]
v10: Code refactoring and using sanitize_target_dc_state(). [Imre]

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Animesh Manna <animesh.manna@intel.com>
Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
Signed-off-by: default avatarAnshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191003081738.22101-4-anshuman.gupta@intel.com
parent 19c79ff8

drivers/gpu/drm/i915/display/intel_display_power.c

+71 −9
Original line number Diff line number Diff line
@@ -769,6 +769,52 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state) 
	dev_priv->csr.dc_state = val & mask;

}



static u32

sanitize_target_dc_state(struct drm_i915_private *dev_priv,

			 u32 target_dc_state)

{

	u32 states[] = {

		DC_STATE_EN_UPTO_DC6,

		DC_STATE_EN_UPTO_DC5,

		DC_STATE_EN_DC3CO,

		DC_STATE_DISABLE,

	};

	int i;



	for (i = 0; i < ARRAY_SIZE(states) - 1; i++) {

		if (target_dc_state != states[i])

			continue;



		if (dev_priv->csr.allowed_dc_mask & target_dc_state)

			break;



		target_dc_state = states[i + 1];

	}



	return target_dc_state;

}



static void tgl_enable_dc3co(struct drm_i915_private *dev_priv)

{

	DRM_DEBUG_KMS("Enabling DC3CO\n");

	gen9_set_dc_state(dev_priv, DC_STATE_EN_DC3CO);

}



static void tgl_disable_dc3co(struct drm_i915_private *dev_priv)

{

	u32 val;



	DRM_DEBUG_KMS("Disabling DC3CO\n");

	val = I915_READ(DC_STATE_EN);

	val &= ~DC_STATE_DC3CO_STATUS;

	I915_WRITE(DC_STATE_EN, val);

	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);

	/*

	 * Delay of 200us DC3CO Exit time B.Spec 49196

	 */

	usleep_range(200, 210);

}



static void bxt_enable_dc9(struct drm_i915_private *dev_priv)

{

	assert_can_enable_dc9(dev_priv);
@@ -936,7 +982,8 @@ static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv) 
static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,

					   struct i915_power_well *power_well)

{

	return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0;

	return ((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 &&

		(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0);

}



static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv)
@@ -952,6 +999,11 @@ static void gen9_disable_dc_states(struct drm_i915_private *dev_priv) 
{

	struct intel_cdclk_state cdclk_state = {};



	if (dev_priv->csr.target_dc_state == DC_STATE_EN_DC3CO) {

		tgl_disable_dc3co(dev_priv);

		return;

	}



	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);



	dev_priv->display.get_cdclk(dev_priv, &cdclk_state);
@@ -984,10 +1036,17 @@ static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv, 
	if (!dev_priv->csr.dmc_payload)

		return;



	if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC6)

	switch (dev_priv->csr.target_dc_state) {

	case DC_STATE_EN_DC3CO:

		tgl_enable_dc3co(dev_priv);

		break;

	case DC_STATE_EN_UPTO_DC6:

		skl_enable_dc6(dev_priv);

	else if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5)

		break;

	case DC_STATE_EN_UPTO_DC5:

		gen9_enable_dc5(dev_priv);

		break;

	}

}



static void i9xx_power_well_sync_hw_noop(struct drm_i915_private *dev_priv,
@@ -2935,7 +2994,7 @@ static const struct i915_power_well_desc skl_power_wells[] = { 
		.name = "DC off",

		.domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,

		.ops = &gen9_dc_off_power_well_ops,

		.id = DISP_PW_ID_NONE,

		.id = SKL_DISP_DC_OFF,

	},

	{

		.name = "power well 2",
@@ -3017,7 +3076,7 @@ static const struct i915_power_well_desc bxt_power_wells[] = { 
		.name = "DC off",

		.domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,

		.ops = &gen9_dc_off_power_well_ops,

		.id = DISP_PW_ID_NONE,

		.id = SKL_DISP_DC_OFF,

	},

	{

		.name = "power well 2",
@@ -3077,7 +3136,7 @@ static const struct i915_power_well_desc glk_power_wells[] = { 
		.name = "DC off",

		.domains = GLK_DISPLAY_DC_OFF_POWER_DOMAINS,

		.ops = &gen9_dc_off_power_well_ops,

		.id = DISP_PW_ID_NONE,

		.id = SKL_DISP_DC_OFF,

	},

	{

		.name = "power well 2",
@@ -3246,7 +3305,7 @@ static const struct i915_power_well_desc cnl_power_wells[] = { 
		.name = "DC off",

		.domains = CNL_DISPLAY_DC_OFF_POWER_DOMAINS,

		.ops = &gen9_dc_off_power_well_ops,

		.id = DISP_PW_ID_NONE,

		.id = SKL_DISP_DC_OFF,

	},

	{

		.name = "power well 2",
@@ -3374,7 +3433,7 @@ static const struct i915_power_well_desc icl_power_wells[] = { 
		.name = "DC off",

		.domains = ICL_DISPLAY_DC_OFF_POWER_DOMAINS,

		.ops = &gen9_dc_off_power_well_ops,

		.id = DISP_PW_ID_NONE,

		.id = SKL_DISP_DC_OFF,

	},

	{

		.name = "power well 2",
@@ -3607,7 +3666,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = { 
		.name = "DC off",

		.domains = TGL_DISPLAY_DC_OFF_POWER_DOMAINS,

		.ops = &gen9_dc_off_power_well_ops,

		.id = DISP_PW_ID_NONE,

		.id = SKL_DISP_DC_OFF,

	},

	{

		.name = "power well 2",
@@ -4040,6 +4099,9 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv) 
	dev_priv->csr.allowed_dc_mask =

		get_allowed_dc_mask(dev_priv, i915_modparams.enable_dc);



	dev_priv->csr.target_dc_state =

		sanitize_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);



	BUILD_BUG_ON(POWER_DOMAIN_NUM > 64);



	mutex_init(&power_domains->lock);

drivers/gpu/drm/i915/display/intel_display_power.h

+1 −0
Original line number Diff line number Diff line
@@ -100,6 +100,7 @@ enum i915_power_well_id { 
	SKL_DISP_PW_MISC_IO,

	SKL_DISP_PW_1,

	SKL_DISP_PW_2,

	SKL_DISP_DC_OFF,

};



#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)

drivers/gpu/drm/i915/i915_drv.h

+1 −0
Original line number Diff line number Diff line
@@ -339,6 +339,7 @@ struct intel_csr { 
	i915_reg_t mmioaddr[20];

	u32 mmiodata[20];

	u32 dc_state;

	u32 target_dc_state;

	u32 allowed_dc_mask;

	intel_wakeref_t wakeref;

};

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