Commit 46374264 authored by Peter Ujfalusi's avatar Peter Ujfalusi Committed by Nishanth Menon
Browse files

arm64: dts: ti: k3-j7200: add DMA support 



Add the ringacc and udmap nodes for Main and MCU NAVSS.

Signed-off-by: default avatarPeter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: default avatarGrygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: default avatarNishanth Menon <nm@ti.com>
Reviewed-by: default avatarSuman Anna <s-anna@ti.com>
Link: https://lore.kernel.org/r/20200923220938.30788-2-grygorii.strashko@ti.com
parent 26bd3f31

arch/arm64/boot/dts/ti/k3-j7200-main.dtsi

+36 −0
Original line number Diff line number Diff line
@@ -93,6 +93,42 @@ 
			interrupt-names = "rx_011";

			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;

		};



		main_ringacc: ringacc@3c000000 {

			compatible = "ti,am654-navss-ringacc";

			reg =	<0x00 0x3c000000 0x00 0x400000>,

				<0x00 0x38000000 0x00 0x400000>,

				<0x00 0x31120000 0x00 0x100>,

				<0x00 0x33000000 0x00 0x40000>;

			reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";

			ti,num-rings = <1024>;

			ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */

			ti,sci = <&dmsc>;

			ti,sci-dev-id = <211>;

			msi-parent = <&main_udmass_inta>;

		};



		main_udmap: dma-controller@31150000 {

			compatible = "ti,j721e-navss-main-udmap";

			reg =	<0x00 0x31150000 0x00 0x100>,

				<0x00 0x34000000 0x00 0x100000>,

				<0x00 0x35000000 0x00 0x100000>;

			reg-names = "gcfg", "rchanrt", "tchanrt";

			msi-parent = <&main_udmass_inta>;

			#dma-cells = <1>;



			ti,sci = <&dmsc>;

			ti,sci-dev-id = <212>;

			ti,ringacc = <&main_ringacc>;



			ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */

						<0x0f>, /* TX_HCHAN */

						<0x10>; /* TX_UHCHAN */

			ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */

						<0x0b>, /* RX_HCHAN */

						<0x0c>; /* RX_UHCHAN */

			ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */

		};

	};



	main_pmx0: pinctrl@11c000 {

arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi

+44 −0
Original line number Diff line number Diff line
@@ -92,4 +92,48 @@ 
		ti,sci-dev-id = <137>;

		ti,interrupt-ranges = <16 960 16>;

	};



	mcu_navss: bus@28380000 {

		compatible = "simple-mfd";

		#address-cells = <2>;

		#size-cells = <2>;

		ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;

		dma-coherent;

		dma-ranges;

		ti,sci-dev-id = <232>;



		mcu_ringacc: ringacc@2b800000 {

			compatible = "ti,am654-navss-ringacc";

			reg =	<0x00 0x2b800000 0x00 0x400000>,

				<0x00 0x2b000000 0x00 0x400000>,

				<0x00 0x28590000 0x00 0x100>,

				<0x00 0x2a500000 0x00 0x40000>;

			reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";

			ti,num-rings = <286>;

			ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */

			ti,sci = <&dmsc>;

			ti,sci-dev-id = <235>;

			msi-parent = <&main_udmass_inta>;

		};



		mcu_udmap: dma-controller@285c0000 {

			compatible = "ti,j721e-navss-mcu-udmap";

			reg =	<0x00 0x285c0000 0x00 0x100>,

				<0x00 0x2a800000 0x00 0x40000>,

				<0x00 0x2aa00000 0x00 0x40000>;

			reg-names = "gcfg", "rchanrt", "tchanrt";

			msi-parent = <&main_udmass_inta>;

			#dma-cells = <1>;



			ti,sci = <&dmsc>;

			ti,sci-dev-id = <236>;

			ti,ringacc = <&mcu_ringacc>;



			ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */

						<0x0f>; /* TX_HCHAN */

			ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */

						<0x0b>; /* RX_HCHAN */

			ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */

		};

	};

};

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