Commit 46097c7d authored by Russell King's avatar Russell King Committed by Russell King
Browse files

[ARM] cachetype: move definitions to separate header 



Rather than pollute asm/cacheflush.h with the cache type definitions,
move them to asm/cachetype.h, and include this new header where
necessary.

Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 0ba8b9b2

arch/arm/include/asm/cacheflush.h

+0 −90
Original line number Diff line number Diff line
@@ -444,94 +444,4 @@ static inline void flush_ioremap_region(unsigned long phys, void __iomem *virt, 
	dmac_inv_range(start, start + size);

}



#define __cacheid_present(val)			(val != read_cpuid(CPUID_ID))

#define __cacheid_type_v7(val)			((val & (7 << 29)) == (4 << 29))



#define __cacheid_vivt_prev7(val)		((val & (15 << 25)) != (14 << 25))

#define __cacheid_vipt_prev7(val)		((val & (15 << 25)) == (14 << 25))

#define __cacheid_vipt_nonaliasing_prev7(val)	((val & (15 << 25 | 1 << 23)) == (14 << 25))

#define __cacheid_vipt_aliasing_prev7(val)	((val & (15 << 25 | 1 << 23)) == (14 << 25 | 1 << 23))



#define __cacheid_vivt(val)			(__cacheid_type_v7(val) ? 0 : __cacheid_vivt_prev7(val))

#define __cacheid_vipt(val)			(__cacheid_type_v7(val) ? 1 : __cacheid_vipt_prev7(val))

#define __cacheid_vipt_nonaliasing(val)		(__cacheid_type_v7(val) ? 1 : __cacheid_vipt_nonaliasing_prev7(val))

#define __cacheid_vipt_aliasing(val)		(__cacheid_type_v7(val) ? 0 : __cacheid_vipt_aliasing_prev7(val))

#define __cacheid_vivt_asid_tagged_instr(val)	(__cacheid_type_v7(val) ? ((val & (3 << 14)) == (1 << 14)) : 0)



#if defined(CONFIG_CPU_CACHE_VIVT) && !defined(CONFIG_CPU_CACHE_VIPT)

/*

 * VIVT caches only

 */

#define cache_is_vivt()			1

#define cache_is_vipt()			0

#define cache_is_vipt_nonaliasing()	0

#define cache_is_vipt_aliasing()	0

#define icache_is_vivt_asid_tagged()	0



#elif !defined(CONFIG_CPU_CACHE_VIVT) && defined(CONFIG_CPU_CACHE_VIPT)

/*

 * VIPT caches only

 */

#define cache_is_vivt()			0

#define cache_is_vipt()			1

#define cache_is_vipt_nonaliasing()					\

	({								\

		unsigned int __val = read_cpuid(CPUID_CACHETYPE);	\

		__cacheid_vipt_nonaliasing(__val);			\

	})



#define cache_is_vipt_aliasing()					\

	({								\

		unsigned int __val = read_cpuid(CPUID_CACHETYPE);	\

		__cacheid_vipt_aliasing(__val);				\

	})



#define icache_is_vivt_asid_tagged()					\

	({								\

		unsigned int __val = read_cpuid(CPUID_CACHETYPE);	\

		__cacheid_vivt_asid_tagged_instr(__val);		\

	})



#else

/*

 * VIVT or VIPT caches.  Note that this is unreliable since ARM926

 * and V6 CPUs satisfy the "(val & (15 << 25)) == (14 << 25)" test.

 * There's no way to tell from the CacheType register what type (!)

 * the cache is.

 */

#define cache_is_vivt()							\

	({								\

		unsigned int __val = read_cpuid(CPUID_CACHETYPE);	\

		(!__cacheid_present(__val)) || __cacheid_vivt(__val);	\

	})

		

#define cache_is_vipt()							\

	({								\

		unsigned int __val = read_cpuid(CPUID_CACHETYPE);	\

		__cacheid_present(__val) && __cacheid_vipt(__val);	\

	})



#define cache_is_vipt_nonaliasing()					\

	({								\

		unsigned int __val = read_cpuid(CPUID_CACHETYPE);	\

		__cacheid_present(__val) &&				\

		 __cacheid_vipt_nonaliasing(__val);			\

	})



#define cache_is_vipt_aliasing()					\

	({								\

		unsigned int __val = read_cpuid(CPUID_CACHETYPE);	\

		__cacheid_present(__val) &&				\

		 __cacheid_vipt_aliasing(__val);			\

	})



#define icache_is_vivt_asid_tagged()					\

	({								\

		unsigned int __val = read_cpuid(CPUID_CACHETYPE);	\

		__cacheid_present(__val) &&				\

		 __cacheid_vivt_asid_tagged_instr(__val);		\

	})



#endif



#endif

arch/arm/include/asm/cachetype.h

0 → 100644
+96 −0
Original line number Diff line number Diff line 
#ifndef __ASM_ARM_CACHETYPE_H

#define __ASM_ARM_CACHETYPE_H



#include <asm/cputype.h>



#define __cacheid_present(val)			(val != read_cpuid_id())

#define __cacheid_type_v7(val)			((val & (7 << 29)) == (4 << 29))



#define __cacheid_vivt_prev7(val)		((val & (15 << 25)) != (14 << 25))

#define __cacheid_vipt_prev7(val)		((val & (15 << 25)) == (14 << 25))

#define __cacheid_vipt_nonaliasing_prev7(val)	((val & (15 << 25 | 1 << 23)) == (14 << 25))

#define __cacheid_vipt_aliasing_prev7(val)	((val & (15 << 25 | 1 << 23)) == (14 << 25 | 1 << 23))



#define __cacheid_vivt(val)			(__cacheid_type_v7(val) ? 0 : __cacheid_vivt_prev7(val))

#define __cacheid_vipt(val)			(__cacheid_type_v7(val) ? 1 : __cacheid_vipt_prev7(val))

#define __cacheid_vipt_nonaliasing(val)		(__cacheid_type_v7(val) ? 1 : __cacheid_vipt_nonaliasing_prev7(val))

#define __cacheid_vipt_aliasing(val)		(__cacheid_type_v7(val) ? 0 : __cacheid_vipt_aliasing_prev7(val))

#define __cacheid_vivt_asid_tagged_instr(val)	(__cacheid_type_v7(val) ? ((val & (3 << 14)) == (1 << 14)) : 0)



#if defined(CONFIG_CPU_CACHE_VIVT) && !defined(CONFIG_CPU_CACHE_VIPT)

/*

 * VIVT caches only

 */

#define cache_is_vivt()			1

#define cache_is_vipt()			0

#define cache_is_vipt_nonaliasing()	0

#define cache_is_vipt_aliasing()	0

#define icache_is_vivt_asid_tagged()	0



#elif !defined(CONFIG_CPU_CACHE_VIVT) && defined(CONFIG_CPU_CACHE_VIPT)

/*

 * VIPT caches only

 */

#define cache_is_vivt()			0

#define cache_is_vipt()			1

#define cache_is_vipt_nonaliasing()					\

	({								\

		unsigned int __val = read_cpuid_cachetype();		\

		__cacheid_vipt_nonaliasing(__val);			\

	})



#define cache_is_vipt_aliasing()					\

	({								\

		unsigned int __val = read_cpuid_cachetype();		\

		__cacheid_vipt_aliasing(__val);				\

	})



#define icache_is_vivt_asid_tagged()					\

	({								\

		unsigned int __val = read_cpuid_cachetype();		\

		__cacheid_vivt_asid_tagged_instr(__val);		\

	})



#else

/*

 * VIVT or VIPT caches.  Note that this is unreliable since ARM926

 * and V6 CPUs satisfy the "(val & (15 << 25)) == (14 << 25)" test.

 * There's no way to tell from the CacheType register what type (!)

 * the cache is.

 */

#define cache_is_vivt()							\

	({								\

		unsigned int __val = read_cpuid_cachetype();		\

		(!__cacheid_present(__val)) || __cacheid_vivt(__val);	\

	})



#define cache_is_vipt()							\

	({								\

		unsigned int __val = read_cpuid_cachetype();		\

		__cacheid_present(__val) && __cacheid_vipt(__val);	\

	})



#define cache_is_vipt_nonaliasing()					\

	({								\

		unsigned int __val = read_cpuid_cachetype();		\

		__cacheid_present(__val) &&				\

		 __cacheid_vipt_nonaliasing(__val);			\

	})



#define cache_is_vipt_aliasing()					\

	({								\

		unsigned int __val = read_cpuid_cachetype();		\

		__cacheid_present(__val) &&				\

		 __cacheid_vipt_aliasing(__val);			\

	})



#define icache_is_vivt_asid_tagged()					\

	({								\

		unsigned int __val = read_cpuid_cachetype();		\

		__cacheid_present(__val) &&				\

		 __cacheid_vivt_asid_tagged_instr(__val);		\

	})



#endif



#endif

arch/arm/include/asm/mmu_context.h

+1 −0
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ 


#include <linux/compiler.h>

#include <asm/cacheflush.h>

#include <asm/cachetype.h>

#include <asm/proc-fns.h>

#include <asm-generic/mm_hooks.h>

arch/arm/kernel/setup.c

+1 −0
Original line number Diff line number Diff line
@@ -32,6 +32,7 @@ 
#include <asm/setup.h>

#include <asm/mach-types.h>

#include <asm/cacheflush.h>

#include <asm/cachetype.h>

#include <asm/tlbflush.h>



#include <asm/mach/arch.h>

arch/arm/mm/copypage-v6.c

+1 −0
Original line number Diff line number Diff line
@@ -16,6 +16,7 @@ 
#include <asm/shmparam.h>

#include <asm/tlbflush.h>

#include <asm/cacheflush.h>

#include <asm/cachetype.h>



#include "mm.h"

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