scsi: be2iscsi: Fix misc static analysis errors (45efc940) · Commits · 戴 / test

drivers/scsi/be2iscsi/be.h

+8 −9

Original line number	Diff line number	Diff line
		@@ -81,12 +81,12 @@ static inline void queue_tail_inc(struct be_queue_info *q)
		/ISCSI /

		struct be_aic_obj { /* Adaptive interrupt coalescing (AIC) info */
		u32 min_eqd; /* in usecs */
		u32 max_eqd; /* in usecs */
		u32 prev_eqd; /* in usecs */
		u32 et_eqd; /* configured val when aic is off */
		ulong jiffies;
		u64 eq_prev; /* Used to calculate eqe */
		unsigned long jiffies;
		u32 eq_prev; /* Used to calculate eqe */
		u32 prev_eqd;
		#define BEISCSI_EQ_DELAY_MIN 0
		#define BEISCSI_EQ_DELAY_DEF 32
		#define BEISCSI_EQ_DELAY_MAX 128
		};

		struct be_eq_obj {
		@@ -150,7 +150,6 @@ struct be_ctrl_info {

		#define PAGE_SHIFT_4K 12
		#define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K)
		#define mcc_timeout 120000 /* 12s timeout */

		/* Returns number of pages spanned by the data starting at the given addr */
		#define PAGES_4K_SPANNED(_address, size) \

drivers/scsi/be2iscsi/be_cmds.c

+0 −1

Original line number	Diff line number	Diff line
		@@ -947,7 +947,6 @@ int beiscsi_cmd_q_destroy(struct be_ctrl_info ctrl, struct be_queue_info q,
		default:
		mutex_unlock(&ctrl->mbox_lock);
		BUG();
		return -ENXIO;
		}
		be_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req));
		if (queue_type != QTYPE_SGL)

drivers/scsi/be2iscsi/be_cmds.h

+2 −12

Original line number	Diff line number	Diff line
		@@ -1298,19 +1298,9 @@ struct be_cmd_get_port_name {
		* a read command
		*/
		#define TGT_CTX_UPDT_CMD 7 /* Target context update */
		#define TGT_STS_CMD 8 /* Target R2T and other BHS
		* where only the status number
		* need to be updated
		*/
		#define TGT_DATAIN_CMD 9 /* Target Data-Ins in response
		* to read command
		*/
		#define TGT_SOS_PDU 10 /* Target:standalone status
		* response
		*/
		#define TGT_DM_CMD 11 /* Indicates that the bhs
		* preparedby
		* driver should not be touched
		* prepared by driver should not
		* be touched.
		*/

		/* Returns the number of items in the field array. */

drivers/scsi/be2iscsi/be_main.c

+17 −23

Original line number	Diff line number	Diff line
		@@ -455,14 +455,12 @@ static int beiscsi_map_pci_bars(struct beiscsi_hba *phba,
		return -ENOMEM;
		phba->ctrl.csr = addr;
		phba->csr_va = addr;
		phba->csr_pa.u.a64.address = pci_resource_start(pcidev, 2);

		addr = ioremap_nocache(pci_resource_start(pcidev, 4), 128 * 1024);
		if (addr == NULL)
		goto pci_map_err;
		phba->ctrl.db = addr;
		phba->db_va = addr;
		phba->db_pa.u.a64.address = pci_resource_start(pcidev, 4);

		if (phba->generation == BE_GEN2)
		pcicfg_reg = 1;
		@@ -476,7 +474,6 @@ static int beiscsi_map_pci_bars(struct beiscsi_hba *phba,
		goto pci_map_err;
		phba->ctrl.pcicfg = addr;
		phba->pci_va = addr;
		phba->pci_pa.u.a64.address = pci_resource_start(pcidev, pcicfg_reg);
		return 0;

		pci_map_err:
		@@ -943,10 +940,9 @@ free_io_sgl_handle(struct beiscsi_hba phba, struct sgl_handle psgl_handle)
		* failed in xmit_task or alloc_pdu.
		*/
		beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO,
		"BM_%d : Double Free in IO SGL io_sgl_free_index=%d,"
		"value there=%p\n", phba->io_sgl_free_index,
		phba->io_sgl_hndl_base
		[phba->io_sgl_free_index]);
		"BM_%d : Double Free in IO SGL io_sgl_free_index=%d, value there=%p\n",
		phba->io_sgl_free_index,
		phba->io_sgl_hndl_base[phba->io_sgl_free_index]);
		spin_unlock_irqrestore(&phba->io_sgl_lock, flags);
		return;
		}
		@@ -1882,8 +1878,8 @@ unsigned int beiscsi_process_cq(struct be_eq_obj *pbe_eq, int budget)

		be_dws_le_to_cpu(sol, sizeof(struct sol_cqe));

		code = (sol->dw[offsetof(struct amap_sol_cqe, code) /
		32] & CQE_CODE_MASK);
		code = (sol->dw[offsetof(struct amap_sol_cqe, code) / 32] &
		CQE_CODE_MASK);

		/* Get the CID */
		if (is_chip_be2_be3r(phba)) {
		@@ -3042,7 +3038,7 @@ static int beiscsi_create_eqs(struct beiscsi_hba *phba,

		mem->dma = paddr;
		ret = beiscsi_cmd_eq_create(&phba->ctrl, eq,
		phwi_context->cur_eqd);
		BEISCSI_EQ_DELAY_DEF);
		if (ret) {
		beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
		"BM_%d : beiscsi_cmd_eq_create"
		@@ -3526,8 +3522,9 @@ static int be_mcc_queues_create(struct beiscsi_hba *phba,
		goto err;
		/* Ask BE to create MCC compl queue; */
		if (phba->pcidev->msix_enabled) {
		if (beiscsi_cmd_cq_create(ctrl, cq, &phwi_context->be_eq
		[phba->num_cpus].q, false, true, 0))
		if (beiscsi_cmd_cq_create(ctrl, cq,
		&phwi_context->be_eq[phba->num_cpus].q,
		false, true, 0))
		goto mcc_cq_free;
		} else {
		if (beiscsi_cmd_cq_create(ctrl, cq, &phwi_context->be_eq[0].q,
		@@ -3707,9 +3704,6 @@ static int hwi_init_port(struct beiscsi_hba *phba)

		phwi_ctrlr = phba->phwi_ctrlr;
		phwi_context = phwi_ctrlr->phwi_ctxt;
		phwi_context->max_eqd = 128;
		phwi_context->min_eqd = 0;
		phwi_context->cur_eqd = 32;
		/* set port optic state to unknown */
		phba->optic_state = 0xff;

		@@ -5234,8 +5228,8 @@ static void beiscsi_eqd_update_work(struct work_struct *work)

		if (eqd < 8)
		eqd = 0;
		eqd = min_t(u32, eqd, phwi_context->max_eqd);
		eqd = max_t(u32, eqd, phwi_context->min_eqd);
		eqd = min_t(u32, eqd, BEISCSI_EQ_DELAY_MAX);
		eqd = max_t(u32, eqd, BEISCSI_EQ_DELAY_MIN);

		aic->jiffies = now;
		aic->eq_prev = pbe_eq->cq_count;

drivers/scsi/be2iscsi/be_main.h

+2 −43

Original line number	Diff line number	Diff line
		@@ -59,7 +59,7 @@
		#define BE2_DEFPDU_DATA_SZ 8192
		#define BE2_MAX_NUM_CQ_PROC 512

		#define MAX_CPUS 64
		#define MAX_CPUS 64U
		#define BEISCSI_MAX_NUM_CPUS 7

		#define BEISCSI_VER_STRLEN 32
		@@ -77,9 +77,7 @@

		#define BEISCSI_MAX_CMD_LEN 16 /* scsi_host->max_cmd_len */
		#define BEISCSI_NUM_MAX_LUN 256 /* scsi_host->max_lun */
		#define BEISCSI_NUM_DEVICES_SUPPORTED 0x01
		#define BEISCSI_MAX_FRAGS_INIT 192
		#define BE_NUM_MSIX_ENTRIES 1

		#define BE_SENSE_INFO_SIZE 258
		#define BE_ISCSI_PDU_HEADER_SIZE 64
		@@ -209,13 +207,8 @@ struct mem_array {
		};

		struct be_mem_descriptor {
		unsigned int index; /* Index of this memory parameter */
		unsigned int category; /* type indicates cached/non-cached */
		unsigned int num_elements; /* number of elements in this
		* descriptor
		*/
		unsigned int alignment_mask; /* Alignment mask for this block */
		unsigned int size_in_bytes; /* Size required by memory block */
		unsigned int num_elements;
		struct mem_array *mem_array;
		};

		@@ -238,32 +231,12 @@ struct hba_parameters {
		unsigned int num_eq_entries;
		unsigned int wrbs_per_cxn;
		unsigned int hwi_ws_sz;
		/**
		* These are calculated from other params. They're here
		* for debug purposes
		*/
		unsigned int num_mcc_pages;
		unsigned int num_mcc_cq_pages;
		unsigned int num_cq_pages;
		unsigned int num_eq_pages;

		unsigned int num_async_pdu_buf_pages;
		unsigned int num_async_pdu_buf_sgl_pages;
		unsigned int num_async_pdu_buf_cq_pages;

		unsigned int num_async_pdu_hdr_pages;
		unsigned int num_async_pdu_hdr_sgl_pages;
		unsigned int num_async_pdu_hdr_cq_pages;

		unsigned int num_sge;
		};

		#define BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr, cri) \
		(phwi_ctrlr->wrb_context[cri].ulp_num)
		struct hwi_wrb_context {
		spinlock_t wrb_lock;
		struct list_head wrb_handle_list;
		struct list_head wrb_handle_drvr_list;
		struct wrb_handle **pwrb_handle_base;
		struct wrb_handle **pwrb_handle_basestd;
		struct iscsi_wrb *plast_wrb;
		@@ -272,8 +245,6 @@ struct hwi_wrb_context {
		unsigned short wrb_handles_available;
		unsigned short cid;
		uint8_t ulp_num; /* ULP to which CID binded */
		uint16_t register_set;
		uint16_t doorbell_format;
		uint32_t doorbell_offset;
		};

		@@ -310,9 +281,6 @@ struct beiscsi_hba {
		u8 __iomem csr_va; / CSR */
		u8 __iomem db_va; / Door Bell */
		u8 __iomem pci_va; / PCI Config */
		struct be_bus_address csr_pa; /* CSR */
		struct be_bus_address db_pa; /* CSR */
		struct be_bus_address pci_pa; /* CSR */
		/* PCI representation of our HBA */
		struct pci_dev *pcidev;
		unsigned int num_cpus;
		@@ -324,7 +292,6 @@ struct beiscsi_hba {
		unsigned short io_sgl_free_index;
		unsigned short io_sgl_hndl_avbl;
		struct sgl_handle **io_sgl_hndl_base;
		struct sgl_handle **sgl_hndl_array;

		unsigned short eh_sgl_alloc_index;
		unsigned short eh_sgl_free_index;
		@@ -1009,10 +976,6 @@ struct be_ring {
		};

		struct hwi_controller {
		struct list_head io_sgl_list;
		struct list_head eh_sgl_list;
		struct sgl_handle *psgl_handle_base;

		struct hwi_wrb_context *wrb_context;
		struct be_ring default_pdu_hdr[BEISCSI_ULP_COUNT];
		struct be_ring default_pdu_data[BEISCSI_ULP_COUNT];
		@@ -1036,10 +999,6 @@ struct wrb_handle {
		};

		struct hwi_context_memory {
		/* Adaptive interrupt coalescing (AIC) info */
		u16 min_eqd; /* in usecs */
		u16 max_eqd; /* in usecs */
		u16 cur_eqd; /* in usecs */
		struct be_eq_obj be_eq[MAX_CPUS];
		struct be_queue_info be_cq[MAX_CPUS - 1];

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