Commit 45cec87c authored by James Zhu's avatar James Zhu Committed by Alex Deucher
Browse files

drm/amdgpu/vcn: move macro from vcn2.0 to share amdgpu_vcn (v2) 



Move macro from vcn2.0 to amdgpu_vcn to share with vcn2.5

v2: squash in macro fix

Signed-off-by: default avatarJames Zhu <James.Zhu@amd.com>
Reviewed-by: default avatarLeo Liu <leo.liu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 5db86843

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

+5 −0
Original line number Diff line number Diff line
@@ -57,6 +57,11 @@ 
#define VCN_VID_IP_ADDRESS_2_0		0x0

#define VCN_AON_IP_ADDRESS_2_0		0x30000



#define mmUVD_RBC_XX_IB_REG_CHECK 					0x026b

#define mmUVD_RBC_XX_IB_REG_CHECK_BASE_IDX 				1

#define mmUVD_REG_XX_MASK 						0x026c

#define mmUVD_REG_XX_MASK_BASE_IDX 					1



/* 1 second timeout */

#define VCN_IDLE_TIMEOUT	msecs_to_jiffies(1000)

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

+7 −7
Original line number Diff line number Diff line
@@ -39,10 +39,10 @@ 
#include "ivsrcid/vcn/irqsrcs_vcn_1_0.h"

#include "jpeg_v1_0.h"



#define mmUVD_RBC_XX_IB_REG_CHECK				0x05ab

#define mmUVD_RBC_XX_IB_REG_CHECK_BASE_IDX	1

#define mmUVD_REG_XX_MASK							0x05ac

#define mmUVD_REG_XX_MASK_BASE_IDX				1

#define mmUVD_RBC_XX_IB_REG_CHECK_1_0		0x05ab

#define mmUVD_RBC_XX_IB_REG_CHECK_1_0_BASE_IDX	1

#define mmUVD_REG_XX_MASK_1_0			0x05ac

#define mmUVD_REG_XX_MASK_1_0_BASE_IDX		1



static int vcn_v1_0_stop(struct amdgpu_device *adev);

static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev);
@@ -835,9 +835,9 @@ static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev) 


	vcn_v1_0_mc_resume_spg_mode(adev);



	WREG32_SOC15(UVD, 0, mmUVD_REG_XX_MASK, 0x10);

	WREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK,

		RREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK) | 0x3);

	WREG32_SOC15(UVD, 0, mmUVD_REG_XX_MASK_1_0, 0x10);

	WREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK_1_0,

		RREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK_1_0) | 0x3);



	/* enable VCPU clock */

	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK);

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

+0 −5
Original line number Diff line number Diff line
@@ -47,11 +47,6 @@ 
#define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET		0x5a7

#define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET			0x1e2



#define mmUVD_RBC_XX_IB_REG_CHECK 					0x026b

#define mmUVD_RBC_XX_IB_REG_CHECK_BASE_IDX 				1

#define mmUVD_REG_XX_MASK 						0x026c

#define mmUVD_REG_XX_MASK_BASE_IDX 					1



static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev);

static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev);

static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev);

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