Commit 45a284bc authored Aug 22, 2018 by Will Deacon Committed by Catalin Marinas Sep 11, 2018

arm64: tlb: Add DSB ISHST prior to TLBI in __flush_tlb_[kernel_]pgtable()



__flush_tlb_[kernel_]pgtable() rely on set_pXd() having a DSB after
writing the new table entry and therefore avoid the barrier prior to the
TLBI instruction.

In preparation for delaying our walk-cache invalidation on the unmap()
path, move the DSB into the TLB invalidation routines.

Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

parent 6899a4c8

arch/arm64/include/asm/tlbflush.h

+2 −0

Original line number	Diff line number	Diff line
		@@ -213,6 +213,7 @@ static inline void __flush_tlb_pgtable(struct mm_struct *mm,
		{
		unsigned long addr = __TLBI_VADDR(uaddr, ASID(mm));

		dsb(ishst);
		__tlbi(vae1is, addr);
		__tlbi_user(vae1is, addr);
		dsb(ish);
		@@ -222,6 +223,7 @@ static inline void __flush_tlb_kernel_pgtable(unsigned long kaddr)
		{
		unsigned long addr = __TLBI_VADDR(kaddr, 0);

		dsb(ishst);
		__tlbi(vaae1is, addr);
		dsb(ish);
		}

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