Merge tag 'x86-timers-2020-03-30' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip (458ef2a2) · Commits · 戴 / test

arch/x86/kernel/tsc_msr.c

+112 −16

Original line number	Diff line number	Diff line
		@@ -15,18 +15,46 @@
		#include <asm/param.h>
		#include <asm/tsc.h>

		#define MAX_NUM_FREQS 9
		#define MAX_NUM_FREQS 16 /* 4 bits to select the frequency */

		/*
		* The frequency numbers in the SDM are e.g. 83.3 MHz, which does not contain a
		* lot of accuracy which leads to clock drift. As far as we know Bay Trail SoCs
		* use a 25 MHz crystal and Cherry Trail uses a 19.2 MHz crystal, the crystal
		* is the source clk for a root PLL which outputs 1600 and 100 MHz. It is
		* unclear if the root PLL outputs are used directly by the CPU clock PLL or
		* if there is another PLL in between.
		* This does not matter though, we can model the chain of PLLs as a single PLL
		* with a quotient equal to the quotients of all PLLs in the chain multiplied.
		* So we can create a simplified model of the CPU clock setup using a reference
		* clock of 100 MHz plus a quotient which gets us as close to the frequency
		* from the SDM as possible.
		* For the 83.3 MHz example from above this would give us 100 MHz * 5 / 6 =
		* 83 and 1/3 MHz, which matches exactly what has been measured on actual hw.
		*/
		#define TSC_REFERENCE_KHZ 100000

		struct muldiv {
		u32 multiplier;
		u32 divider;
		};

		/*
		* If MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be
		* read in MSR_PLATFORM_ID[12:8], otherwise in MSR_PERF_STAT[44:40].
		* Unfortunately some Intel Atom SoCs aren't quite compliant to this,
		* so we need manually differentiate SoC families. This is what the
		* field msr_plat does.
		* field use_msr_plat does.
		*/
		struct freq_desc {
		u8 msr_plat; /* 1: use MSR_PLATFORM_INFO, 0: MSR_IA32_PERF_STATUS */
		bool use_msr_plat;
		struct muldiv muldiv[MAX_NUM_FREQS];
		/*
		* Some CPU frequencies in the SDM do not map to known PLL freqs, in
		* that case the muldiv array is empty and the freqs array is used.
		*/
		u32 freqs[MAX_NUM_FREQS];
		u32 mask;
		};

		/*
		@@ -35,31 +63,81 @@ struct freq_desc {
		* by MSR based on SDM.
		*/
		static const struct freq_desc freq_desc_pnw = {
		0, { 0, 0, 0, 0, 0, 99840, 0, 83200 }
		.use_msr_plat = false,
		.freqs = { 0, 0, 0, 0, 0, 99840, 0, 83200 },
		.mask = 0x07,
		};

		static const struct freq_desc freq_desc_clv = {
		0, { 0, 133200, 0, 0, 0, 99840, 0, 83200 }
		.use_msr_plat = false,
		.freqs = { 0, 133200, 0, 0, 0, 99840, 0, 83200 },
		.mask = 0x07,
		};

		/*
		* Bay Trail SDM MSR_FSB_FREQ frequencies simplified PLL model:
		* 000: 100 * 5 / 6 = 83.3333 MHz
		* 001: 100 * 1 / 1 = 100.0000 MHz
		* 010: 100 * 4 / 3 = 133.3333 MHz
		* 011: 100 * 7 / 6 = 116.6667 MHz
		* 100: 100 * 4 / 5 = 80.0000 MHz
		*/
		static const struct freq_desc freq_desc_byt = {
		1, { 83300, 100000, 133300, 116700, 80000, 0, 0, 0 }
		.use_msr_plat = true,
		.muldiv = { { 5, 6 }, { 1, 1 }, { 4, 3 }, { 7, 6 },
		{ 4, 5 } },
		.mask = 0x07,
		};

		/*
		* Cherry Trail SDM MSR_FSB_FREQ frequencies simplified PLL model:
		* 0000: 100 * 5 / 6 = 83.3333 MHz
		* 0001: 100 * 1 / 1 = 100.0000 MHz
		* 0010: 100 * 4 / 3 = 133.3333 MHz
		* 0011: 100 * 7 / 6 = 116.6667 MHz
		* 0100: 100 * 4 / 5 = 80.0000 MHz
		* 0101: 100 * 14 / 15 = 93.3333 MHz
		* 0110: 100 * 9 / 10 = 90.0000 MHz
		* 0111: 100 * 8 / 9 = 88.8889 MHz
		* 1000: 100 * 7 / 8 = 87.5000 MHz
		*/
		static const struct freq_desc freq_desc_cht = {
		1, { 83300, 100000, 133300, 116700, 80000, 93300, 90000, 88900, 87500 }
		.use_msr_plat = true,
		.muldiv = { { 5, 6 }, { 1, 1 }, { 4, 3 }, { 7, 6 },
		{ 4, 5 }, { 14, 15 }, { 9, 10 }, { 8, 9 },
		{ 7, 8 } },
		.mask = 0x0f,
		};

		/*
		* Merriefield SDM MSR_FSB_FREQ frequencies simplified PLL model:
		* 0001: 100 * 1 / 1 = 100.0000 MHz
		* 0010: 100 * 4 / 3 = 133.3333 MHz
		*/
		static const struct freq_desc freq_desc_tng = {
		1, { 0, 100000, 133300, 0, 0, 0, 0, 0 }
		.use_msr_plat = true,
		.muldiv = { { 0, 0 }, { 1, 1 }, { 4, 3 } },
		.mask = 0x07,
		};

		/*
		* Moorefield SDM MSR_FSB_FREQ frequencies simplified PLL model:
		* 0000: 100 * 5 / 6 = 83.3333 MHz
		* 0001: 100 * 1 / 1 = 100.0000 MHz
		* 0010: 100 * 4 / 3 = 133.3333 MHz
		* 0011: 100 * 1 / 1 = 100.0000 MHz
		*/
		static const struct freq_desc freq_desc_ann = {
		1, { 83300, 100000, 133300, 100000, 0, 0, 0, 0 }
		.use_msr_plat = true,
		.muldiv = { { 5, 6 }, { 1, 1 }, { 4, 3 }, { 1, 1 } },
		.mask = 0x0f,
		};

		/* 24 MHz crystal? : 24 * 13 / 4 = 78 MHz */
		static const struct freq_desc freq_desc_lgm = {
		1, { 78000, 78000, 78000, 78000, 78000, 78000, 78000, 78000 }
		.use_msr_plat = true,
		.freqs = { 78000, 78000, 78000, 78000, 78000, 78000, 78000, 78000 },
		.mask = 0x0f,
		};

		static const struct x86_cpu_id tsc_msr_cpu_ids[] = {
		@@ -81,17 +159,19 @@ static const struct x86_cpu_id tsc_msr_cpu_ids[] = {
		*/
		unsigned long cpu_khz_from_msr(void)
		{
		u32 lo, hi, ratio, freq;
		u32 lo, hi, ratio, freq, tscref;
		const struct freq_desc *freq_desc;
		const struct x86_cpu_id *id;
		const struct muldiv *md;
		unsigned long res;
		int index;

		id = x86_match_cpu(tsc_msr_cpu_ids);
		if (!id)
		return 0;

		freq_desc = (struct freq_desc *)id->driver_data;
		if (freq_desc->msr_plat) {
		if (freq_desc->use_msr_plat) {
		rdmsr(MSR_PLATFORM_INFO, lo, hi);
		ratio = (lo >> 8) & 0xff;
		} else {
		@@ -101,12 +181,28 @@ unsigned long cpu_khz_from_msr(void)

		/* Get FSB FREQ ID */
		rdmsr(MSR_FSB_FREQ, lo, hi);
		index = lo & freq_desc->mask;
		md = &freq_desc->muldiv[index];

		/* Map CPU reference clock freq ID(0-7) to CPU reference clock freq(KHz) */
		freq = freq_desc->freqs[lo & 0x7];

		/* TSC frequency = maximum resolved freq * maximum resolved bus ratio */
		/*
		* Note this also catches cases where the index points to an unpopulated
		* part of muldiv, in that case the else will set freq and res to 0.
		*/
		if (md->divider) {
		tscref = TSC_REFERENCE_KHZ * md->multiplier;
		freq = DIV_ROUND_CLOSEST(tscref, md->divider);
		/*
		* Multiplying by ratio before the division has better
		* accuracy than just calculating freq * ratio.
		*/
		res = DIV_ROUND_CLOSEST(tscref * ratio, md->divider);
		} else {
		freq = freq_desc->freqs[index];
		res = freq * ratio;
		}

		if (freq == 0)
		pr_err("Error MSR_FSB_FREQ index %d is unknown\n", index);

		#ifdef CONFIG_X86_LOCAL_APIC
		lapic_timer_period = (freq * 1000) / HZ;

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