drm/bridge: ti-sn65dsi86: Read num lanes from the DP sink (457622d9) · Commits · 戴 / test

drivers/gpu/drm/bridge/ti-sn65dsi86.c

+30 −2

Original line number	Diff line number	Diff line
		@@ -313,8 +313,7 @@ static int ti_sn_bridge_attach(struct drm_bridge *bridge)
		goto err_dsi_host;
		}

		/* TODO: setting to 4 lanes always for now */
		pdata->dp_lanes = 4;
		/* TODO: setting to 4 MIPI lanes always for now */
		dsi->lanes = 4;
		dsi->format = MIPI_DSI_FMT_RGB888;
		dsi->mode_flags = MIPI_DSI_MODE_VIDEO;
		@@ -511,12 +510,41 @@ static void ti_sn_bridge_set_video_timings(struct ti_sn_bridge *pdata)
		usleep_range(10000, 10500); /* 10ms delay recommended by spec */
		}

		static unsigned int ti_sn_get_max_lanes(struct ti_sn_bridge *pdata)
		{
		u8 data;
		int ret;

		ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LANE_COUNT, &data);
		if (ret != 1) {
		DRM_DEV_ERROR(pdata->dev,
		"Can't read lane count (%d); assuming 4\n", ret);
		return 4;
		}

		return data & DP_LANE_COUNT_MASK;
		}

		static void ti_sn_bridge_enable(struct drm_bridge *bridge)
		{
		struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
		unsigned int val;
		int ret;

		/*
		* Run with the maximum number of lanes that the DP sink supports.
		*
		* Depending use cases, we might want to revisit this later because:
		* - It's plausible that someone may have run fewer lines to the
		* sink than the sink actually supports, assuming that the lines
		* will just be driven at a higher rate.
		* - The DP spec seems to indicate that it's more important to minimize
		* the number of lanes than the link rate.
		*
		* If we do revisit, it would be important to measure the power impact.
		*/
		pdata->dp_lanes = ti_sn_get_max_lanes(pdata);

		/* DSI_A lane config */
		val = CHA_DSI_LANES(4 - pdata->dsi->lanes);
		regmap_update_bits(pdata->regmap, SN_DSI_LANES_REG,

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