Commit 45682886 authored by Monk Liu's avatar Monk Liu Committed by Alex Deucher
Browse files

drm/amdgpu:impl vgt_flush for VI(V5) 



when shadowing enabled, tesselation app will trigger
vm fault because below three tesselation registers:

VGT_TF_RING_SIZE__CI__VI,
VGT_HS_OFFCHIP_PARAM__CI__VI,
VGT_TF_MEMORY_BASE__CI__VI,

need to be programed after vgt-flush.

Tesselation picture vm fault disappeared after vgt-flush
introduced.

v2:implement vgt-flush for CI & SI.
v3:move vgt flush inside of cntx_cntrl
v4:count vgt flush in frame_size
v5:squash in typo fix

Signed-off-by: default avatarMonk Liu <Monk.Liu@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 79abf1ad

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

+32 −23
Original line number Diff line number Diff line
@@ -1463,6 +1463,13 @@ static void gfx_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 
	amdgpu_ring_write(ring, 0x1);

}



static void gfx_v6_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)

{

	amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));

	amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) |

		EVENT_INDEX(0));

}



/**

 * gfx_v6_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp

 *
@@ -2802,6 +2809,8 @@ static uint64_t gfx_v6_0_get_gpu_clock_counter(struct amdgpu_device *adev) 


static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)

{

	if (flags & AMDGPU_HAVE_CTX_SWITCH)

		gfx_v6_0_ring_emit_vgt_flush(ring);

	amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));

	amdgpu_ring_write(ring, 0x80000000);

	amdgpu_ring_write(ring, 0);
@@ -3265,7 +3274,7 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = { 
		14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */

		7 + 4 + /* gfx_v6_0_ring_emit_pipeline_sync */

		17 + 6 + /* gfx_v6_0_ring_emit_vm_flush */

		3, /* gfx_v6_ring_emit_cntxcntl */

		3 + 2, /* gfx_v6_ring_emit_cntxcntl including vgt flush */

	.emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */

	.emit_ib = gfx_v6_0_ring_emit_ib,

	.emit_fence = gfx_v6_0_ring_emit_fence,

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

+14 −1
Original line number Diff line number Diff line
@@ -2105,6 +2105,18 @@ static void gfx_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 
	amdgpu_ring_write(ring, 0x20); /* poll interval */

}



static void gfx_v7_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)

{

	amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));

	amdgpu_ring_write(ring, EVENT_TYPE(VS_PARTIAL_FLUSH) |

		EVENT_INDEX(4));



	amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));

	amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) |

		EVENT_INDEX(0));

}





/**

 * gfx_v7_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp

 *
@@ -2260,6 +2272,7 @@ static void gfx_v7_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) 


	dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */

	if (flags & AMDGPU_HAVE_CTX_SWITCH) {

		gfx_v7_0_ring_emit_vgt_flush(ring);

		/* set load_global_config & load_global_uconfig */

		dw2 |= 0x8001;

		/* set load_cs_sh_regs */
@@ -5153,7 +5166,7 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = { 
		12 + 12 + 12 + /* gfx_v7_0_ring_emit_fence_gfx x3 for user fence, vm fence */

		7 + 4 + /* gfx_v7_0_ring_emit_pipeline_sync */

		17 + 6 + /* gfx_v7_0_ring_emit_vm_flush */

		3, /* gfx_v7_ring_emit_cntxcntl */

		3 + 4, /* gfx_v7_ring_emit_cntxcntl including vgt flush*/

	.emit_ib_size = 4, /* gfx_v7_0_ring_emit_ib_gfx */

	.emit_ib = gfx_v7_0_ring_emit_ib_gfx,

	.emit_fence = gfx_v7_0_ring_emit_fence_gfx,

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

+14 −1
Original line number Diff line number Diff line
@@ -6186,6 +6186,18 @@ static void gfx_v8_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 
	amdgpu_ring_write(ring, 0x20); /* poll interval */

}



static void gfx_v8_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)

{

	amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));

	amdgpu_ring_write(ring, EVENT_TYPE(VS_PARTIAL_FLUSH) |

		EVENT_INDEX(4));



	amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));

	amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) |

		EVENT_INDEX(0));

}





static void gfx_v8_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)

{

	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
@@ -6371,6 +6383,7 @@ static void gfx_v8_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) 


	dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */

	if (flags & AMDGPU_HAVE_CTX_SWITCH) {

		gfx_v8_0_ring_emit_vgt_flush(ring);

		/* set load_global_config & load_global_uconfig */

		dw2 |= 0x8001;

		/* set load_cs_sh_regs */
@@ -6574,7 +6587,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = { 
		7 + /* gfx_v8_0_ring_emit_pipeline_sync */

		128 + 19 + /* gfx_v8_0_ring_emit_vm_flush */

		2 + /* gfx_v8_ring_emit_sb */

		3, /* gfx_v8_ring_emit_cntxcntl */

		3 + 4, /* gfx_v8_ring_emit_cntxcntl including vgt flush */

	.emit_ib_size =	4, /* gfx_v8_0_ring_emit_ib_gfx */

	.emit_ib = gfx_v8_0_ring_emit_ib_gfx,

	.emit_fence = gfx_v8_0_ring_emit_fence_gfx,

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