soc/tegra: pmc: Configure core power request polarity (455271d9) · Commits · 戴 / test

This patch configures polarity of the core power request signal in PMC control register based on the device tree property. PMC asserts and de-asserts power request signal based on it polarity when it need to power-up and power-down the core rail during SC7. Reviewed-by:

Dmitry Osipenko <digetx@gmail.com> Signed-off-by:

Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by:

Thierry Reding <treding@nvidia.com>

drivers/soc/tegra/pmc.c

+6 −0

Original line number	Diff line number	Diff line
		@@ -56,6 +56,7 @@
		#define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */
		#define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */
		#define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */
		#define PMC_CNTRL_PWRREQ_POLARITY BIT(8)
		#define PMC_CNTRL_MAIN_RST BIT(4)

		#define PMC_WAKE_MASK 0x0c
		@@ -2316,6 +2317,11 @@ static void tegra20_pmc_init(struct tegra_pmc *pmc)
		else
		value \|= PMC_CNTRL_SYSCLK_POLARITY;

		if (pmc->corereq_high)
		value &= ~PMC_CNTRL_PWRREQ_POLARITY;
		else
		value \|= PMC_CNTRL_PWRREQ_POLARITY;

		/* configure the output polarity while the request is tristated */
		tegra_pmc_writel(pmc, value, PMC_CNTRL);

Admin message