Commit 454854ac authored by Aleksandar Markovic's avatar Aleksandar Markovic Committed by Ralf Baechle
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MIPS: math-emu: Add FP emu debugfs stats for individual instructions 



Add FP emulation debugfs statistics for individual instructions. The
debugfs files that contain counter values are placed in a separate
directory called "instructions". This means that the default path for
these new stat is "/sys/kernel/debug/mips/fpuemustats/instructions".

Each instruction counter is mapped to the debugfs file that has the
same name as instruction name. The lowercase is choosen as more
commonly used case for instruction names.

One example of usage:

mips_host::/sys/kernel/debug/mips/fpuemustats/instructions # grep "" *

The shortened output of this command is:

abs.d:34
abs.s:5711
add.d:10401
add.s:399307
bc1eqz:3199
...
...
...
sub.s:167211
trunc.l.d:375
trunc.l.s:8054
trunc.w.d:421
trunc.w.s:27032

The limitation of this patch is that it handles R6 FP emulation
instructions only. There are altogether 114 handled instructions.

Signed-off-by: default avatarMiodrag Dinic <miodrag.dinic@imgtec.com>
Signed-off-by: default avatarGoran Ferenc <goran.ferenc@imgtec.com>
Signed-off-by: default avatarAleksandar Markovic <aleksandar.markovic@imgtec.com>
Cc: Douglas Leung <douglas.leung@imgtec.com>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: Maciej W. Rozycki <macro@imgtec.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Petar Jovanovic <petar.jovanovic@imgtec.com>
Cc: Raghu Gandham <raghu.gandham@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/17145/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 25ad8db6

arch/mips/include/asm/fpu_emulator.h

+115 −0
Original line number Diff line number Diff line
@@ -46,6 +46,121 @@ struct mips_fpu_emulator_stats { 
	unsigned long ieee754_zerodiv;

	unsigned long ieee754_invalidop;

	unsigned long ds_emul;



	unsigned long abs_s;

	unsigned long abs_d;

	unsigned long add_s;

	unsigned long add_d;

	unsigned long bc1eqz;

	unsigned long bc1nez;

	unsigned long ceil_w_s;

	unsigned long ceil_w_d;

	unsigned long ceil_l_s;

	unsigned long ceil_l_d;

	unsigned long class_s;

	unsigned long class_d;

	unsigned long cmp_af_s;

	unsigned long cmp_af_d;

	unsigned long cmp_eq_s;

	unsigned long cmp_eq_d;

	unsigned long cmp_le_s;

	unsigned long cmp_le_d;

	unsigned long cmp_lt_s;

	unsigned long cmp_lt_d;

	unsigned long cmp_ne_s;

	unsigned long cmp_ne_d;

	unsigned long cmp_or_s;

	unsigned long cmp_or_d;

	unsigned long cmp_ueq_s;

	unsigned long cmp_ueq_d;

	unsigned long cmp_ule_s;

	unsigned long cmp_ule_d;

	unsigned long cmp_ult_s;

	unsigned long cmp_ult_d;

	unsigned long cmp_un_s;

	unsigned long cmp_un_d;

	unsigned long cmp_une_s;

	unsigned long cmp_une_d;

	unsigned long cmp_saf_s;

	unsigned long cmp_saf_d;

	unsigned long cmp_seq_s;

	unsigned long cmp_seq_d;

	unsigned long cmp_sle_s;

	unsigned long cmp_sle_d;

	unsigned long cmp_slt_s;

	unsigned long cmp_slt_d;

	unsigned long cmp_sne_s;

	unsigned long cmp_sne_d;

	unsigned long cmp_sor_s;

	unsigned long cmp_sor_d;

	unsigned long cmp_sueq_s;

	unsigned long cmp_sueq_d;

	unsigned long cmp_sule_s;

	unsigned long cmp_sule_d;

	unsigned long cmp_sult_s;

	unsigned long cmp_sult_d;

	unsigned long cmp_sun_s;

	unsigned long cmp_sun_d;

	unsigned long cmp_sune_s;

	unsigned long cmp_sune_d;

	unsigned long cvt_d_l;

	unsigned long cvt_d_s;

	unsigned long cvt_d_w;

	unsigned long cvt_l_s;

	unsigned long cvt_l_d;

	unsigned long cvt_s_d;

	unsigned long cvt_s_l;

	unsigned long cvt_s_w;

	unsigned long cvt_w_s;

	unsigned long cvt_w_d;

	unsigned long div_s;

	unsigned long div_d;

	unsigned long floor_w_s;

	unsigned long floor_w_d;

	unsigned long floor_l_s;

	unsigned long floor_l_d;

	unsigned long maddf_s;

	unsigned long maddf_d;

	unsigned long max_s;

	unsigned long max_d;

	unsigned long maxa_s;

	unsigned long maxa_d;

	unsigned long min_s;

	unsigned long min_d;

	unsigned long mina_s;

	unsigned long mina_d;

	unsigned long mov_s;

	unsigned long mov_d;

	unsigned long msubf_s;

	unsigned long msubf_d;

	unsigned long mul_s;

	unsigned long mul_d;

	unsigned long neg_s;

	unsigned long neg_d;

	unsigned long recip_s;

	unsigned long recip_d;

	unsigned long rint_s;

	unsigned long rint_d;

	unsigned long round_w_s;

	unsigned long round_w_d;

	unsigned long round_l_s;

	unsigned long round_l_d;

	unsigned long rsqrt_s;

	unsigned long rsqrt_d;

	unsigned long sel_s;

	unsigned long sel_d;

	unsigned long seleqz_s;

	unsigned long seleqz_d;

	unsigned long selnez_s;

	unsigned long selnez_d;

	unsigned long sqrt_s;

	unsigned long sqrt_d;

	unsigned long sub_s;

	unsigned long sub_d;

	unsigned long trunc_w_s;

	unsigned long trunc_w_d;

	unsigned long trunc_l_s;

	unsigned long trunc_l_d;

};



DECLARE_PER_CPU(struct mips_fpu_emulator_stats, fpuemustats);

arch/mips/math-emu/cp1emu.c

+258 −0
Original line number Diff line number Diff line
@@ -1195,9 +1195,11 @@ emul: 
			bit0 = get_fpr32(fpr, 0) & 0x1;

			switch (MIPSInst_RS(ir)) {

			case bc1eqz_op:

				MIPS_FPU_EMU_INC_STATS(bc1eqz);

				cond = bit0 == 0;

				break;

			case bc1nez_op:

				MIPS_FPU_EMU_INC_STATS(bc1nez);

				cond = bit0 != 0;

				break;

			}
@@ -1683,15 +1685,19 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 
		switch (MIPSInst_FUNC(ir)) {

			/* binary ops */

		case fadd_op:

			MIPS_FPU_EMU_INC_STATS(add_s);

			handler.b = ieee754sp_add;

			goto scopbop;

		case fsub_op:

			MIPS_FPU_EMU_INC_STATS(sub_s);

			handler.b = ieee754sp_sub;

			goto scopbop;

		case fmul_op:

			MIPS_FPU_EMU_INC_STATS(mul_s);

			handler.b = ieee754sp_mul;

			goto scopbop;

		case fdiv_op:

			MIPS_FPU_EMU_INC_STATS(div_s);

			handler.b = ieee754sp_div;

			goto scopbop;
@@ -1700,6 +1706,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 
			if (!cpu_has_mips_2_3_4_5_r)

				return SIGILL;



			MIPS_FPU_EMU_INC_STATS(sqrt_s);

			handler.u = ieee754sp_sqrt;

			goto scopuop;
@@ -1712,6 +1719,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 
			if (!cpu_has_mips_4_5_64_r2_r6)

				return SIGILL;



			MIPS_FPU_EMU_INC_STATS(rsqrt_s);

			handler.u = fpemu_sp_rsqrt;

			goto scopuop;
@@ -1719,6 +1727,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 
			if (!cpu_has_mips_4_5_64_r2_r6)

				return SIGILL;



			MIPS_FPU_EMU_INC_STATS(recip_s);

			handler.u = fpemu_sp_recip;

			goto scopuop;
@@ -1755,6 +1764,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 
			if (!cpu_has_mips_r6)

				return SIGILL;



			MIPS_FPU_EMU_INC_STATS(seleqz_s);

			SPFROMREG(rv.s, MIPSInst_FT(ir));

			if (rv.w & 0x1)

				rv.w = 0;
@@ -1766,6 +1776,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 
			if (!cpu_has_mips_r6)

				return SIGILL;



			MIPS_FPU_EMU_INC_STATS(selnez_s);

			SPFROMREG(rv.s, MIPSInst_FT(ir));

			if (rv.w & 0x1)

				SPFROMREG(rv.s, MIPSInst_FS(ir));
@@ -1779,6 +1790,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 
			if (!cpu_has_mips_r6)

				return SIGILL;



			MIPS_FPU_EMU_INC_STATS(maddf_s);

			SPFROMREG(ft, MIPSInst_FT(ir));

			SPFROMREG(fs, MIPSInst_FS(ir));

			SPFROMREG(fd, MIPSInst_FD(ir));
@@ -1792,6 +1804,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 
			if (!cpu_has_mips_r6)

				return SIGILL;



			MIPS_FPU_EMU_INC_STATS(msubf_s);

			SPFROMREG(ft, MIPSInst_FT(ir));

			SPFROMREG(fs, MIPSInst_FS(ir));

			SPFROMREG(fd, MIPSInst_FD(ir));
@@ -1805,6 +1818,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 
			if (!cpu_has_mips_r6)

				return SIGILL;



			MIPS_FPU_EMU_INC_STATS(rint_s);

			SPFROMREG(fs, MIPSInst_FS(ir));

			rv.s = ieee754sp_rint(fs);

			goto copcsr;
@@ -1816,6 +1830,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 
			if (!cpu_has_mips_r6)

				return SIGILL;



			MIPS_FPU_EMU_INC_STATS(class_s);

			SPFROMREG(fs, MIPSInst_FS(ir));

			rv.w = ieee754sp_2008class(fs);

			rfmt = w_fmt;
@@ -1828,6 +1843,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 
			if (!cpu_has_mips_r6)

				return SIGILL;



			MIPS_FPU_EMU_INC_STATS(min_s);

			SPFROMREG(ft, MIPSInst_FT(ir));

			SPFROMREG(fs, MIPSInst_FS(ir));

			rv.s = ieee754sp_fmin(fs, ft);
@@ -1840,6 +1856,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 
			if (!cpu_has_mips_r6)

				return SIGILL;



			MIPS_FPU_EMU_INC_STATS(mina_s);

			SPFROMREG(ft, MIPSInst_FT(ir));

			SPFROMREG(fs, MIPSInst_FS(ir));

			rv.s = ieee754sp_fmina(fs, ft);
@@ -1852,6 +1869,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 
			if (!cpu_has_mips_r6)

				return SIGILL;



			MIPS_FPU_EMU_INC_STATS(max_s);

			SPFROMREG(ft, MIPSInst_FT(ir));

			SPFROMREG(fs, MIPSInst_FS(ir));

			rv.s = ieee754sp_fmax(fs, ft);
@@ -1864,6 +1882,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 
			if (!cpu_has_mips_r6)

				return SIGILL;



			MIPS_FPU_EMU_INC_STATS(maxa_s);

			SPFROMREG(ft, MIPSInst_FT(ir));

			SPFROMREG(fs, MIPSInst_FS(ir));

			rv.s = ieee754sp_fmaxa(fs, ft);
@@ -1871,15 +1890,18 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 
		}



		case fabs_op:

			MIPS_FPU_EMU_INC_STATS(abs_s);

			handler.u = ieee754sp_abs;

			goto scopuop;



		case fneg_op:

			MIPS_FPU_EMU_INC_STATS(neg_s);

			handler.u = ieee754sp_neg;

			goto scopuop;



		case fmov_op:

			/* an easy one */

			MIPS_FPU_EMU_INC_STATS(mov_s);

			SPFROMREG(rv.s, MIPSInst_FS(ir));

			goto copcsr;
@@ -1922,12 +1944,14 @@ copcsr: 
			return SIGILL;	/* not defined */



		case fcvtd_op:

			MIPS_FPU_EMU_INC_STATS(cvt_d_s);

			SPFROMREG(fs, MIPSInst_FS(ir));

			rv.d = ieee754dp_fsp(fs);

			rfmt = d_fmt;

			goto copcsr;



		case fcvtw_op:

			MIPS_FPU_EMU_INC_STATS(cvt_w_s);

			SPFROMREG(fs, MIPSInst_FS(ir));

			rv.w = ieee754sp_tint(fs);

			rfmt = w_fmt;
@@ -1940,6 +1964,15 @@ copcsr: 
			if (!cpu_has_mips_2_3_4_5_r)

				return SIGILL;



			if (MIPSInst_FUNC(ir) == fceil_op)

				MIPS_FPU_EMU_INC_STATS(ceil_w_s);

			if (MIPSInst_FUNC(ir) == ffloor_op)

				MIPS_FPU_EMU_INC_STATS(floor_w_s);

			if (MIPSInst_FUNC(ir) == fround_op)

				MIPS_FPU_EMU_INC_STATS(round_w_s);

			if (MIPSInst_FUNC(ir) == ftrunc_op)

				MIPS_FPU_EMU_INC_STATS(trunc_w_s);



			oldrm = ieee754_csr.rm;

			SPFROMREG(fs, MIPSInst_FS(ir));

			ieee754_csr.rm = MIPSInst_FUNC(ir);
@@ -1952,6 +1985,7 @@ copcsr: 
			if (!cpu_has_mips_r6)

				return SIGILL;



			MIPS_FPU_EMU_INC_STATS(sel_s);

			SPFROMREG(fd, MIPSInst_FD(ir));

			if (fd.bits & 0x1)

				SPFROMREG(rv.s, MIPSInst_FT(ir));
@@ -1963,6 +1997,7 @@ copcsr: 
			if (!cpu_has_mips_3_4_5_64_r2_r6)

				return SIGILL;



			MIPS_FPU_EMU_INC_STATS(cvt_l_s);

			SPFROMREG(fs, MIPSInst_FS(ir));

			rv.l = ieee754sp_tlong(fs);

			rfmt = l_fmt;
@@ -1975,6 +2010,15 @@ copcsr: 
			if (!cpu_has_mips_3_4_5_64_r2_r6)

				return SIGILL;



			if (MIPSInst_FUNC(ir) == fceill_op)

				MIPS_FPU_EMU_INC_STATS(ceil_l_s);

			if (MIPSInst_FUNC(ir) == ffloorl_op)

				MIPS_FPU_EMU_INC_STATS(floor_l_s);

			if (MIPSInst_FUNC(ir) == froundl_op)

				MIPS_FPU_EMU_INC_STATS(round_l_s);

			if (MIPSInst_FUNC(ir) == ftruncl_op)

				MIPS_FPU_EMU_INC_STATS(trunc_l_s);



			oldrm = ieee754_csr.rm;

			SPFROMREG(fs, MIPSInst_FS(ir));

			ieee754_csr.rm = MIPSInst_FUNC(ir);
@@ -2016,15 +2060,19 @@ copcsr: 
		switch (MIPSInst_FUNC(ir)) {

			/* binary ops */

		case fadd_op:

			MIPS_FPU_EMU_INC_STATS(add_d);

			handler.b = ieee754dp_add;

			goto dcopbop;

		case fsub_op:

			MIPS_FPU_EMU_INC_STATS(sub_d);

			handler.b = ieee754dp_sub;

			goto dcopbop;

		case fmul_op:

			MIPS_FPU_EMU_INC_STATS(mul_d);

			handler.b = ieee754dp_mul;

			goto dcopbop;

		case fdiv_op:

			MIPS_FPU_EMU_INC_STATS(div_d);

			handler.b = ieee754dp_div;

			goto dcopbop;
@@ -2033,6 +2081,7 @@ copcsr: 
			if (!cpu_has_mips_2_3_4_5_r)

				return SIGILL;



			MIPS_FPU_EMU_INC_STATS(sqrt_d);

			handler.u = ieee754dp_sqrt;

			goto dcopuop;

		/*
@@ -2044,12 +2093,14 @@ copcsr: 
			if (!cpu_has_mips_4_5_64_r2_r6)

				return SIGILL;



			MIPS_FPU_EMU_INC_STATS(rsqrt_d);

			handler.u = fpemu_dp_rsqrt;

			goto dcopuop;

		case frecip_op:

			if (!cpu_has_mips_4_5_64_r2_r6)

				return SIGILL;



			MIPS_FPU_EMU_INC_STATS(recip_d);

			handler.u = fpemu_dp_recip;

			goto dcopuop;

		case fmovc_op:
@@ -2083,6 +2134,7 @@ copcsr: 
			if (!cpu_has_mips_r6)

				return SIGILL;



			MIPS_FPU_EMU_INC_STATS(seleqz_d);

			DPFROMREG(rv.d, MIPSInst_FT(ir));

			if (rv.l & 0x1)

				rv.l = 0;
@@ -2094,6 +2146,7 @@ copcsr: 
			if (!cpu_has_mips_r6)

				return SIGILL;



			MIPS_FPU_EMU_INC_STATS(selnez_d);

			DPFROMREG(rv.d, MIPSInst_FT(ir));

			if (rv.l & 0x1)

				DPFROMREG(rv.d, MIPSInst_FS(ir));
@@ -2107,6 +2160,7 @@ copcsr: 
			if (!cpu_has_mips_r6)

				return SIGILL;



			MIPS_FPU_EMU_INC_STATS(maddf_d);

			DPFROMREG(ft, MIPSInst_FT(ir));

			DPFROMREG(fs, MIPSInst_FS(ir));

			DPFROMREG(fd, MIPSInst_FD(ir));
@@ -2120,6 +2174,7 @@ copcsr: 
			if (!cpu_has_mips_r6)

				return SIGILL;



			MIPS_FPU_EMU_INC_STATS(msubf_d);

			DPFROMREG(ft, MIPSInst_FT(ir));

			DPFROMREG(fs, MIPSInst_FS(ir));

			DPFROMREG(fd, MIPSInst_FD(ir));
@@ -2133,6 +2188,7 @@ copcsr: 
			if (!cpu_has_mips_r6)

				return SIGILL;



			MIPS_FPU_EMU_INC_STATS(rint_d);

			DPFROMREG(fs, MIPSInst_FS(ir));

			rv.d = ieee754dp_rint(fs);

			goto copcsr;
@@ -2144,6 +2200,7 @@ copcsr: 
			if (!cpu_has_mips_r6)

				return SIGILL;



			MIPS_FPU_EMU_INC_STATS(class_d);

			DPFROMREG(fs, MIPSInst_FS(ir));

			rv.l = ieee754dp_2008class(fs);

			rfmt = l_fmt;
@@ -2156,6 +2213,7 @@ copcsr: 
			if (!cpu_has_mips_r6)

				return SIGILL;



			MIPS_FPU_EMU_INC_STATS(min_d);

			DPFROMREG(ft, MIPSInst_FT(ir));

			DPFROMREG(fs, MIPSInst_FS(ir));

			rv.d = ieee754dp_fmin(fs, ft);
@@ -2168,6 +2226,7 @@ copcsr: 
			if (!cpu_has_mips_r6)

				return SIGILL;



			MIPS_FPU_EMU_INC_STATS(mina_d);

			DPFROMREG(ft, MIPSInst_FT(ir));

			DPFROMREG(fs, MIPSInst_FS(ir));

			rv.d = ieee754dp_fmina(fs, ft);
@@ -2180,6 +2239,7 @@ copcsr: 
			if (!cpu_has_mips_r6)

				return SIGILL;



			MIPS_FPU_EMU_INC_STATS(max_d);

			DPFROMREG(ft, MIPSInst_FT(ir));

			DPFROMREG(fs, MIPSInst_FS(ir));

			rv.d = ieee754dp_fmax(fs, ft);
@@ -2192,6 +2252,7 @@ copcsr: 
			if (!cpu_has_mips_r6)

				return SIGILL;



			MIPS_FPU_EMU_INC_STATS(maxa_d);

			DPFROMREG(ft, MIPSInst_FT(ir));

			DPFROMREG(fs, MIPSInst_FS(ir));

			rv.d = ieee754dp_fmaxa(fs, ft);
@@ -2199,15 +2260,18 @@ copcsr: 
		}



		case fabs_op:

			MIPS_FPU_EMU_INC_STATS(abs_d);

			handler.u = ieee754dp_abs;

			goto dcopuop;



		case fneg_op:

			MIPS_FPU_EMU_INC_STATS(neg_d);

			handler.u = ieee754dp_neg;

			goto dcopuop;



		case fmov_op:

			/* an easy one */

			MIPS_FPU_EMU_INC_STATS(mov_d);

			DPFROMREG(rv.d, MIPSInst_FS(ir));

			goto copcsr;
@@ -2227,6 +2291,7 @@ dcopuop: 
		 * unary conv ops

		 */

		case fcvts_op:

			MIPS_FPU_EMU_INC_STATS(cvt_s_d);

			DPFROMREG(fs, MIPSInst_FS(ir));

			rv.s = ieee754sp_fdp(fs);

			rfmt = s_fmt;
@@ -2236,6 +2301,7 @@ dcopuop: 
			return SIGILL;	/* not defined */



		case fcvtw_op:

			MIPS_FPU_EMU_INC_STATS(cvt_w_d);

			DPFROMREG(fs, MIPSInst_FS(ir));

			rv.w = ieee754dp_tint(fs);	/* wrong */

			rfmt = w_fmt;
@@ -2248,6 +2314,15 @@ dcopuop: 
			if (!cpu_has_mips_2_3_4_5_r)

				return SIGILL;



			if (MIPSInst_FUNC(ir) == fceil_op)

				MIPS_FPU_EMU_INC_STATS(ceil_w_d);

			if (MIPSInst_FUNC(ir) == ffloor_op)

				MIPS_FPU_EMU_INC_STATS(floor_w_d);

			if (MIPSInst_FUNC(ir) == fround_op)

				MIPS_FPU_EMU_INC_STATS(round_w_d);

			if (MIPSInst_FUNC(ir) == ftrunc_op)

				MIPS_FPU_EMU_INC_STATS(trunc_w_d);



			oldrm = ieee754_csr.rm;

			DPFROMREG(fs, MIPSInst_FS(ir));

			ieee754_csr.rm = MIPSInst_FUNC(ir);
@@ -2260,6 +2335,7 @@ dcopuop: 
			if (!cpu_has_mips_r6)

				return SIGILL;



			MIPS_FPU_EMU_INC_STATS(sel_d);

			DPFROMREG(fd, MIPSInst_FD(ir));

			if (fd.bits & 0x1)

				DPFROMREG(rv.d, MIPSInst_FT(ir));
@@ -2271,6 +2347,7 @@ dcopuop: 
			if (!cpu_has_mips_3_4_5_64_r2_r6)

				return SIGILL;



			MIPS_FPU_EMU_INC_STATS(cvt_l_d);

			DPFROMREG(fs, MIPSInst_FS(ir));

			rv.l = ieee754dp_tlong(fs);

			rfmt = l_fmt;
@@ -2283,6 +2360,15 @@ dcopuop: 
			if (!cpu_has_mips_3_4_5_64_r2_r6)

				return SIGILL;



			if (MIPSInst_FUNC(ir) == fceill_op)

				MIPS_FPU_EMU_INC_STATS(ceil_l_d);

			if (MIPSInst_FUNC(ir) == ffloorl_op)

				MIPS_FPU_EMU_INC_STATS(floor_l_d);

			if (MIPSInst_FUNC(ir) == froundl_op)

				MIPS_FPU_EMU_INC_STATS(round_l_d);

			if (MIPSInst_FUNC(ir) == ftruncl_op)

				MIPS_FPU_EMU_INC_STATS(trunc_l_d);



			oldrm = ieee754_csr.rm;

			DPFROMREG(fs, MIPSInst_FS(ir));

			ieee754_csr.rm = MIPSInst_FUNC(ir);
@@ -2324,12 +2410,14 @@ dcopuop: 
		switch (MIPSInst_FUNC(ir)) {

		case fcvts_op:

			/* convert word to single precision real */

			MIPS_FPU_EMU_INC_STATS(cvt_s_w);

			SPFROMREG(fs, MIPSInst_FS(ir));

			rv.s = ieee754sp_fint(fs.bits);

			rfmt = s_fmt;

			goto copcsr;

		case fcvtd_op:

			/* convert word to double precision real */

			MIPS_FPU_EMU_INC_STATS(cvt_d_w);

			SPFROMREG(fs, MIPSInst_FS(ir));

			rv.d = ieee754dp_fint(fs.bits);

			rfmt = d_fmt;
@@ -2349,6 +2437,90 @@ dcopuop: 
			    (MIPSInst_FUNC(ir) & 0x20))

				return SIGILL;



			if (!sig) {

				if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {

					switch (cmpop) {

					case 0:

					MIPS_FPU_EMU_INC_STATS(cmp_af_s);

					break;

					case 1:

					MIPS_FPU_EMU_INC_STATS(cmp_un_s);

					break;

					case 2:

					MIPS_FPU_EMU_INC_STATS(cmp_eq_s);

					break;

					case 3:

					MIPS_FPU_EMU_INC_STATS(cmp_ueq_s);

					break;

					case 4:

					MIPS_FPU_EMU_INC_STATS(cmp_lt_s);

					break;

					case 5:

					MIPS_FPU_EMU_INC_STATS(cmp_ult_s);

					break;

					case 6:

					MIPS_FPU_EMU_INC_STATS(cmp_le_s);

					break;

					case 7:

					MIPS_FPU_EMU_INC_STATS(cmp_ule_s);

					break;

					}

				} else {

					switch (cmpop) {

					case 1:

					MIPS_FPU_EMU_INC_STATS(cmp_or_s);

					break;

					case 2:

					MIPS_FPU_EMU_INC_STATS(cmp_une_s);

					break;

					case 3:

					MIPS_FPU_EMU_INC_STATS(cmp_ne_s);

					break;

					}

				}

			} else {

				if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {

					switch (cmpop) {

					case 0:

					MIPS_FPU_EMU_INC_STATS(cmp_saf_s);

					break;

					case 1:

					MIPS_FPU_EMU_INC_STATS(cmp_sun_s);

					break;

					case 2:

					MIPS_FPU_EMU_INC_STATS(cmp_seq_s);

					break;

					case 3:

					MIPS_FPU_EMU_INC_STATS(cmp_sueq_s);

					break;

					case 4:

					MIPS_FPU_EMU_INC_STATS(cmp_slt_s);

					break;

					case 5:

					MIPS_FPU_EMU_INC_STATS(cmp_sult_s);

					break;

					case 6:

					MIPS_FPU_EMU_INC_STATS(cmp_sle_s);

					break;

					case 7:

					MIPS_FPU_EMU_INC_STATS(cmp_sule_s);

					break;

					}

				} else {

					switch (cmpop) {

					case 1:

					MIPS_FPU_EMU_INC_STATS(cmp_sor_s);

					break;

					case 2:

					MIPS_FPU_EMU_INC_STATS(cmp_sune_s);

					break;

					case 3:

					MIPS_FPU_EMU_INC_STATS(cmp_sne_s);

					break;

					}

				}

			}



			/* fmt is w_fmt for single precision so fix it */

			rfmt = s_fmt;

			/* default to false */
@@ -2406,11 +2578,13 @@ dcopuop: 
		switch (MIPSInst_FUNC(ir)) {

		case fcvts_op:

			/* convert long to single precision real */

			MIPS_FPU_EMU_INC_STATS(cvt_s_l);

			rv.s = ieee754sp_flong(bits);

			rfmt = s_fmt;

			goto copcsr;

		case fcvtd_op:

			/* convert long to double precision real */

			MIPS_FPU_EMU_INC_STATS(cvt_d_l);

			rv.d = ieee754dp_flong(bits);

			rfmt = d_fmt;

			goto copcsr;
@@ -2424,6 +2598,90 @@ dcopuop: 
			    (MIPSInst_FUNC(ir) & 0x20))

				return SIGILL;



			if (!sig) {

				if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {

					switch (cmpop) {

					case 0:

					MIPS_FPU_EMU_INC_STATS(cmp_af_d);

					break;

					case 1:

					MIPS_FPU_EMU_INC_STATS(cmp_un_d);

					break;

					case 2:

					MIPS_FPU_EMU_INC_STATS(cmp_eq_d);

					break;

					case 3:

					MIPS_FPU_EMU_INC_STATS(cmp_ueq_d);

					break;

					case 4:

					MIPS_FPU_EMU_INC_STATS(cmp_lt_d);

					break;

					case 5:

					MIPS_FPU_EMU_INC_STATS(cmp_ult_d);

					break;

					case 6:

					MIPS_FPU_EMU_INC_STATS(cmp_le_d);

					break;

					case 7:

					MIPS_FPU_EMU_INC_STATS(cmp_ule_d);

					break;

					}

				} else {

					switch (cmpop) {

					case 1:

					MIPS_FPU_EMU_INC_STATS(cmp_or_d);

					break;

					case 2:

					MIPS_FPU_EMU_INC_STATS(cmp_une_d);

					break;

					case 3:

					MIPS_FPU_EMU_INC_STATS(cmp_ne_d);

					break;

					}

				}

			} else {

				if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {

					switch (cmpop) {

					case 0:

					MIPS_FPU_EMU_INC_STATS(cmp_saf_d);

					break;

					case 1:

					MIPS_FPU_EMU_INC_STATS(cmp_sun_d);

					break;

					case 2:

					MIPS_FPU_EMU_INC_STATS(cmp_seq_d);

					break;

					case 3:

					MIPS_FPU_EMU_INC_STATS(cmp_sueq_d);

					break;

					case 4:

					MIPS_FPU_EMU_INC_STATS(cmp_slt_d);

					break;

					case 5:

					MIPS_FPU_EMU_INC_STATS(cmp_sult_d);

					break;

					case 6:

					MIPS_FPU_EMU_INC_STATS(cmp_sle_d);

					break;

					case 7:

					MIPS_FPU_EMU_INC_STATS(cmp_sule_d);

					break;

					}

				} else {

					switch (cmpop) {

					case 1:

					MIPS_FPU_EMU_INC_STATS(cmp_sor_d);

					break;

					case 2:

					MIPS_FPU_EMU_INC_STATS(cmp_sune_d);

					break;

					case 3:

					MIPS_FPU_EMU_INC_STATS(cmp_sne_d);

					break;

					}

				}

			}



			/* fmt is l_fmt for double precision so fix it */

			rfmt = d_fmt;

			/* default to false */

arch/mips/math-emu/me-debugfs.c

+277 −4

File changed.

Preview size limit exceeded, changes collapsed.

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