+5
−2
Loading
Gitlab 现已全面支持 git over ssh 与 git over https。通过 HTTPS 访问请配置带有 read_repository / write_repository 权限的 Personal access token。通过 SSH 端口访问请使用 22 端口或 13389 端口。如果使用CAS注册了账户但不知道密码,可以自行至设置中更改;如有其他问题,请发邮件至 service@cra.moe 寻求协助。
USB 3.2 specification adds a Gen XxY notion for USB3 devices where X is the signaling rate on the wire. Gen 1xY is 5Gbps Superspeed and Gen 2xY is 10Gbps SuperSpeedPlus. Y is the lane count. For normal, non inter-chip (SSIC) devies the rx and tx lane count is symmetric, and the maximum lane count for USB 3.2 devices is 2 (dual-lane). SSIC devices may have asymmetric lane counts, with up to four lanes per direction. The USB 3.2 specification doesn't point out how to use the Gen XxY notion for these devices, so we limit the Gen Xx2 notion to symmertic Dual lane devies. For other devices just show Gen1 or Gen2 Gen 1 5Gbps Gen 2 10Gbps Gen 1x2 10Gbps Dual-lane (USB 3.2) Gen 2x2 20Gbps Dual-lane (USB 3.2) Signed-off-by:Mathias Nyman <mathias.nyman@linux.intel.com> Signed-off-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org>
CRA Git | Maintained and supported by SUSTech CRA and CCSE