Commit 45361a4f authored by Thomas Petazzoni's avatar Thomas Petazzoni Committed by Jason Cooper
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pci: PCIe driver for Marvell Armada 370/XP systems 



This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.

The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.

Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.

In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.

Signed-off-by: default avatarThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Signed-off-by: default avatarJason Cooper <jason@lakedaemon.net>
parent a5e69879

Documentation/devicetree/bindings/pci/mvebu-pci.txt

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* Marvell EBU PCIe interfaces



Mandatory properties:

- compatible: one of the following values:

    marvell,armada-370-pcie

    marvell,armada-xp-pcie

- #address-cells, set to <3>

- #size-cells, set to <2>

- #interrupt-cells, set to <1>

- bus-range: PCI bus numbers covered

- device_type, set to "pci"

- ranges: ranges for the PCI memory and I/O regions, as well as the

  MMIO registers to control the PCIe interfaces.



In addition, the Device Tree node must have sub-nodes describing each

PCIe interface, having the following mandatory properties:

- reg: used only for interrupt mapping, so only the first four bytes

  are used to refer to the correct bus number and device number.

- assigned-addresses: reference to the MMIO registers used to control

  this PCIe interface.

- clocks: the clock associated to this PCIe interface

- marvell,pcie-port: the physical PCIe port number

- status: either "disabled" or "okay"

- device_type, set to "pci"

- #address-cells, set to <3>

- #size-cells, set to <2>

- #interrupt-cells, set to <1>

- ranges, empty property.

- interrupt-map-mask and interrupt-map, standard PCI properties to

  define the mapping of the PCIe interface to interrupt numbers.



and the following optional properties:

- marvell,pcie-lane: the physical PCIe lane number, for ports having

  multiple lanes. If this property is not found, we assume that the

  value is 0.



Example:



pcie-controller {

	compatible = "marvell,armada-xp-pcie";

	status = "disabled";

	device_type = "pci";



	#address-cells = <3>;

	#size-cells = <2>;



	bus-range = <0x00 0xff>;



	ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000   /* Port 0.0 registers */

		  0x82000000 0 0xd0042000 0xd0042000 0 0x00002000   /* Port 2.0 registers */

		  0x82000000 0 0xd0044000 0xd0044000 0 0x00002000   /* Port 0.1 registers */

		  0x82000000 0 0xd0048000 0xd0048000 0 0x00002000   /* Port 0.2 registers */

		  0x82000000 0 0xd004c000 0xd004c000 0 0x00002000   /* Port 0.3 registers */

		  0x82000000 0 0xd0080000 0xd0080000 0 0x00002000   /* Port 1.0 registers */

		  0x82000000 0 0xd0082000 0xd0082000 0 0x00002000   /* Port 3.0 registers */

		  0x82000000 0 0xd0084000 0xd0084000 0 0x00002000   /* Port 1.1 registers */

		  0x82000000 0 0xd0088000 0xd0088000 0 0x00002000   /* Port 1.2 registers */

		  0x82000000 0 0xd008c000 0xd008c000 0 0x00002000   /* Port 1.3 registers */

		  0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */

		  0x81000000 0 0	  0xe8000000 0 0x00100000>; /* downstream I/O */



	pcie@1,0 {

		device_type = "pci";

		assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>;

		reg = <0x0800 0 0 0 0>;

		#address-cells = <3>;

		#size-cells = <2>;

		#interrupt-cells = <1>;

		ranges;

		interrupt-map-mask = <0 0 0 0>;

		interrupt-map = <0 0 0 0 &mpic 58>;

		marvell,pcie-port = <0>;

		marvell,pcie-lane = <0>;

		clocks = <&gateclk 5>;

		status = "disabled";

	};



	pcie@2,0 {

		device_type = "pci";

		assigned-addresses = <0x82001000 0 0xd0044000 0 0x2000>;

		reg = <0x1000 0 0 0 0>;

		#address-cells = <3>;

		#size-cells = <2>;

		#interrupt-cells = <1>;

		ranges;

		interrupt-map-mask = <0 0 0 0>;

		interrupt-map = <0 0 0 0 &mpic 59>;

		marvell,pcie-port = <0>;

		marvell,pcie-lane = <1>;

		clocks = <&gateclk 6>;

		status = "disabled";

	};



	pcie@3,0 {

		device_type = "pci";

		assigned-addresses = <0x82001800 0 0xd0048000 0 0x2000>;

		reg = <0x1800 0 0 0 0>;

		#address-cells = <3>;

		#size-cells = <2>;

		#interrupt-cells = <1>;

		ranges;

		interrupt-map-mask = <0 0 0 0>;

		interrupt-map = <0 0 0 0 &mpic 60>;

		marvell,pcie-port = <0>;

		marvell,pcie-lane = <2>;

		clocks = <&gateclk 7>;

		status = "disabled";

	};



	pcie@4,0 {

		device_type = "pci";

		assigned-addresses = <0x82002000 0 0xd004c000 0 0x2000>;

		reg = <0x2000 0 0 0 0>;

		#address-cells = <3>;

		#size-cells = <2>;

		#interrupt-cells = <1>;

		ranges;

		interrupt-map-mask = <0 0 0 0>;

		interrupt-map = <0 0 0 0 &mpic 61>;

		marvell,pcie-port = <0>;

		marvell,pcie-lane = <3>;

		clocks = <&gateclk 8>;

		status = "disabled";

	};



	pcie@5,0 {

		device_type = "pci";

		assigned-addresses = <0x82002800 0 0xd0080000 0 0x2000>;

		reg = <0x2800 0 0 0 0>;

		#address-cells = <3>;

		#size-cells = <2>;

		#interrupt-cells = <1>;

		ranges;

		interrupt-map-mask = <0 0 0 0>;

		interrupt-map = <0 0 0 0 &mpic 62>;

		marvell,pcie-port = <1>;

		marvell,pcie-lane = <0>;

		clocks = <&gateclk 9>;

		status = "disabled";

	};



	pcie@6,0 {

		device_type = "pci";

		assigned-addresses = <0x82003000 0 0xd0084000 0 0x2000>;

		reg = <0x3000 0 0 0 0>;

		#address-cells = <3>;

		#size-cells = <2>;

		#interrupt-cells = <1>;

		ranges;

		interrupt-map-mask = <0 0 0 0>;

		interrupt-map = <0 0 0 0 &mpic 63>;

		marvell,pcie-port = <1>;

		marvell,pcie-lane = <1>;

		clocks = <&gateclk 10>;

		status = "disabled";

	};



	pcie@7,0 {

		device_type = "pci";

		assigned-addresses = <0x82003800 0 0xd0088000 0 0x2000>;

		reg = <0x3800 0 0 0 0>;

		#address-cells = <3>;

		#size-cells = <2>;

		#interrupt-cells = <1>;

		ranges;

		interrupt-map-mask = <0 0 0 0>;

		interrupt-map = <0 0 0 0 &mpic 64>;

		marvell,pcie-port = <1>;

		marvell,pcie-lane = <2>;

		clocks = <&gateclk 11>;

		status = "disabled";

	};



	pcie@8,0 {

		device_type = "pci";

		assigned-addresses = <0x82004000 0 0xd008c000 0 0x2000>;

		reg = <0x4000 0 0 0 0>;

		#address-cells = <3>;

		#size-cells = <2>;

		#interrupt-cells = <1>;

		ranges;

		interrupt-map-mask = <0 0 0 0>;

		interrupt-map = <0 0 0 0 &mpic 65>;

		marvell,pcie-port = <1>;

		marvell,pcie-lane = <3>;

		clocks = <&gateclk 12>;

		status = "disabled";

	};

	pcie@9,0 {

		device_type = "pci";

		assigned-addresses = <0x82004800 0 0xd0042000 0 0x2000>;

		reg = <0x4800 0 0 0 0>;

		#address-cells = <3>;

		#size-cells = <2>;

		#interrupt-cells = <1>;

		ranges;

		interrupt-map-mask = <0 0 0 0>;

		interrupt-map = <0 0 0 0 &mpic 99>;

		marvell,pcie-port = <2>;

		marvell,pcie-lane = <0>;

		clocks = <&gateclk 26>;

		status = "disabled";

	};



	pcie@10,0 {

		device_type = "pci";

		assigned-addresses = <0x82005000 0 0xd0082000 0 0x2000>;

		reg = <0x5000 0 0 0 0>;

		#address-cells = <3>;

		#size-cells = <2>;

		#interrupt-cells = <1>;

		ranges;

		interrupt-map-mask = <0 0 0 0>;

		interrupt-map = <0 0 0 0 &mpic 103>;

		marvell,pcie-port = <3>;

		marvell,pcie-lane = <0>;

		clocks = <&gateclk 27>;

		status = "disabled";

	};

};

drivers/pci/Kconfig

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@@ -119,3 +119,5 @@ config PCI_IOAPIC 
config PCI_LABEL

	def_bool y if (DMI || ACPI)

	select NLS



source "drivers/pci/host/Kconfig"

drivers/pci/Makefile

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@@ -67,3 +67,6 @@ obj-$(CONFIG_XEN_PCIDEV_FRONTEND) += xen-pcifront.o 
obj-$(CONFIG_OF) += of.o



ccflags-$(CONFIG_PCI_DEBUG) := -DDEBUG



# PCI host controller drivers

obj-y += host/

drivers/pci/host/Kconfig

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menu "PCI host controller drivers"

	depends on PCI



config PCI_MVEBU

	bool "Marvell EBU PCIe controller"

	depends on ARCH_MVEBU



endmenu

drivers/pci/host/Makefile

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obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o

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