Commit 451555c8 authored by Roger Quadros's avatar Roger Quadros Committed by Tero Kristo
Browse files

arm64: dts: ti: k3-j721e-main: add USB controller nodes 



J721e has 2 USB super-speed controllers add them.

The USB2 PHY doesn't need any configuration.
USB3 PHY needs to be implemented using the Cadence
Sierra PHY. This support will be added later.

Signed-off-by: default avatarRoger Quadros <rogerq@ti.com>
Signed-off-by: default avatarSekhar Nori <nsekhar@ti.com>
Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
parent 337c4a88

arch/arm64/boot/dts/ti/k3-j721e-main.dtsi

+60 −0
Original line number Diff line number Diff line
@@ -536,4 +536,64 @@ 
		dma-coherent;

		no-1-8-v;

	};



	usbss0: cdns_usb@4104000 {

		compatible = "ti,j721e-usb";

		reg = <0x00 0x4104000 0x00 0x100>;

		dma-coherent;

		power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;

		clocks = <&k3_clks 288 15>, <&k3_clks 288 3>;

		clock-names = "ref", "lpm";

		assigned-clocks = <&k3_clks 288 15>;	/* USB2_REFCLK */

		assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */

		#address-cells = <2>;

		#size-cells = <2>;

		ranges;



		usb0: usb@6000000 {

			compatible = "cdns,usb3";

			reg = <0x00 0x6000000 0x00 0x10000>,

			      <0x00 0x6010000 0x00 0x10000>,

			      <0x00 0x6020000 0x00 0x10000>;

			reg-names = "otg", "xhci", "dev";

			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,	/* irq.0 */

				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,	/* irq.6 */

				     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;	/* otgirq.0 */

			interrupt-names = "host",

					  "peripheral",

					  "otg";

			maximum-speed = "super-speed";

			dr_mode = "otg";

		};

	};



	usbss1: cdns_usb@4114000 {

		compatible = "ti,j721e-usb";

		reg = <0x00 0x4114000 0x00 0x100>;

		dma-coherent;

		power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>;

		clocks = <&k3_clks 289 15>, <&k3_clks 289 3>;

		clock-names = "ref", "lpm";

		assigned-clocks = <&k3_clks 289 15>;	/* USB2_REFCLK */

		assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */

		#address-cells = <2>;

		#size-cells = <2>;

		ranges;



		usb1: usb@6400000 {

			compatible = "cdns,usb3";

			reg = <0x00 0x6400000 0x00 0x10000>,

			      <0x00 0x6410000 0x00 0x10000>,

			      <0x00 0x6420000 0x00 0x10000>;

			reg-names = "otg", "xhci", "dev";

			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,	/* irq.0 */

				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,	/* irq.6 */

				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;	/* otgirq.0 */

			interrupt-names = "host",

					  "peripheral",

					  "otg";

			maximum-speed = "super-speed";

			dr_mode = "otg";

		};

	};

};

arch/arm64/boot/dts/ti/k3-j721e.dtsi

+2 −0
Original line number Diff line number Diff line
@@ -127,6 +127,8 @@ 
			 <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */

			 <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */

			 <0x00 0x00A40000 0x00 0x00A40000 0x00 0x00000800>, /* timesync router */

			 <0x00 0x06000000 0x00 0x06000000 0x00 0x00400000>, /* USBSS0 */

			 <0x00 0x06400000 0x00 0x06400000 0x00 0x00400000>, /* USBSS1 */

			 <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */

			 <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */

			 <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01000000>, /* PCIe Core*/

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