Commit 450da2ef authored by James Zhu's avatar James Zhu Committed by Alex Deucher
Browse files

drm/amdgpu: fix unused variable 



SOC15_WAIT_ON_RREG's return value needn't always been handled by
caller. new design is to fix this kind of unused variable.

Signed-off-by: default avatarJames Zhu <James.Zhu@amd.com>
Reported-by: default avatarkernel test robot <lkp@intel.com>
Acked-by: default avatarLeo Liu <leo.liu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent a20ace1b

drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c

+7 −7
Original line number Diff line number Diff line
@@ -230,9 +230,9 @@ static int jpeg_v2_0_disable_power_gating(struct amdgpu_device *adev) 
		data = 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;

		WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);



		SOC15_WAIT_ON_RREG(JPEG, 0,

		r = SOC15_WAIT_ON_RREG(JPEG, 0,

			mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS_UVDJ_PWR_ON,

			UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK, r);

			UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK);



		if (r) {

			DRM_ERROR("amdgpu: JPEG disable power gating failed\n");
@@ -261,9 +261,9 @@ static int jpeg_v2_0_enable_power_gating(struct amdgpu_device* adev) 
		data = 2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;

		WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);



		SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_PGFSM_STATUS,

		r = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_PGFSM_STATUS,

			(2 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT),

			UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK, r);

			UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK);



		if (r) {

			DRM_ERROR("amdgpu: JPEG enable power gating failed\n");
@@ -677,10 +677,10 @@ static bool jpeg_v2_0_is_idle(void *handle) 
static int jpeg_v2_0_wait_for_idle(void *handle)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	int ret = 0;

	int ret;



	SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_JRBC_STATUS, UVD_JRBC_STATUS__RB_JOB_DONE_MASK,

		UVD_JRBC_STATUS__RB_JOB_DONE_MASK, ret);

	ret = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_JRBC_STATUS, UVD_JRBC_STATUS__RB_JOB_DONE_MASK,

		UVD_JRBC_STATUS__RB_JOB_DONE_MASK);



	return ret;

}

drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c

+3 −3
Original line number Diff line number Diff line
@@ -449,15 +449,15 @@ static bool jpeg_v2_5_is_idle(void *handle) 
static int jpeg_v2_5_wait_for_idle(void *handle)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	int i, ret = 0;

	int i, ret;



	for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {

		if (adev->jpeg.harvest_config & (1 << i))

			continue;



		SOC15_WAIT_ON_RREG(JPEG, i, mmUVD_JRBC_STATUS,

		ret = SOC15_WAIT_ON_RREG(JPEG, i, mmUVD_JRBC_STATUS,

			UVD_JRBC_STATUS__RB_JOB_DONE_MASK,

			UVD_JRBC_STATUS__RB_JOB_DONE_MASK, ret);

			UVD_JRBC_STATUS__RB_JOB_DONE_MASK);

		if (ret)

			return ret;

	}

drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c

+7 −7
Original line number Diff line number Diff line
@@ -266,9 +266,9 @@ static int jpeg_v3_0_disable_static_power_gating(struct amdgpu_device *adev) 
		data = 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;

		WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);



		SOC15_WAIT_ON_RREG(JPEG, 0,

		r = SOC15_WAIT_ON_RREG(JPEG, 0,

			mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS_UVDJ_PWR_ON,

			UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK, r);

			UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK);



		if (r) {

			DRM_ERROR("amdgpu: JPEG disable power gating failed\n");
@@ -301,9 +301,9 @@ static int jpeg_v3_0_enable_static_power_gating(struct amdgpu_device* adev) 
		data = 2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;

		WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);



		SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_PGFSM_STATUS,

		r = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_PGFSM_STATUS,

			(2 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT),

			UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK, r);

			UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK);



		if (r) {

			DRM_ERROR("amdgpu: JPEG enable power gating failed\n");
@@ -461,11 +461,11 @@ static bool jpeg_v3_0_is_idle(void *handle) 
static int jpeg_v3_0_wait_for_idle(void *handle)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	int ret = 0;

	int ret;



	SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_JRBC_STATUS,

	ret = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_JRBC_STATUS,

		UVD_JRBC_STATUS__RB_JOB_DONE_MASK,

		UVD_JRBC_STATUS__RB_JOB_DONE_MASK, ret);

		UVD_JRBC_STATUS__RB_JOB_DONE_MASK);

	if (ret)

		return ret;

drivers/gpu/drm/amd/amdgpu/soc15_common.h

+9 −6
Original line number Diff line number Diff line
@@ -50,7 +50,8 @@ 
#define WREG32_SOC15_OFFSET(ip, inst, reg, offset, value) \

	WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, value)



#define SOC15_WAIT_ON_RREG(ip, inst, reg, expected_value, mask, ret) \

#define SOC15_WAIT_ON_RREG(ip, inst, reg, expected_value, mask) \

({	int ret = 0;						\

	do {							\

		uint32_t old_ = 0;				\

		uint32_t tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \
@@ -71,7 +72,9 @@ 
				break;				\

			}					\

		}						\

	} while (0)

	} while (0);						\

	ret;							\

})



#define WREG32_RLC(reg, value) \

	do {							\

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

+24 −27
Original line number Diff line number Diff line
@@ -683,7 +683,6 @@ static void vcn_v1_0_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t s 
static void vcn_1_0_disable_static_power_gating(struct amdgpu_device *adev)

{

	uint32_t data = 0;

	int ret;



	if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {

		data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
@@ -699,7 +698,7 @@ static void vcn_1_0_disable_static_power_gating(struct amdgpu_device *adev) 
			| 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT);



		WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);

		SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON, 0xFFFFFF, ret);

		SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON, 0xFFFFFF);

	} else {

		data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT

			| 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
@@ -713,7 +712,7 @@ static void vcn_1_0_disable_static_power_gating(struct amdgpu_device *adev) 
			| 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT

			| 1 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT);

		WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);

		SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0,  0xFFFFFFFF, ret);

		SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0,  0xFFFFFFFF);

	}



	/* polling UVD_PGFSM_STATUS to confirm UVDM_PWR_STATUS , UVDU_PWR_STATUS are 0 (power on) */
@@ -729,7 +728,6 @@ static void vcn_1_0_disable_static_power_gating(struct amdgpu_device *adev) 
static void vcn_1_0_enable_static_power_gating(struct amdgpu_device *adev)

{

	uint32_t data = 0;

	int ret;



	if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {

		/* Before power off, this indicator has to be turned on */
@@ -764,7 +762,7 @@ static void vcn_1_0_enable_static_power_gating(struct amdgpu_device *adev) 
			| 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT

			| 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT

			| 2 << UVD_PGFSM_STATUS__UVDW_PWR_STATUS__SHIFT);

		SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFFFFF, ret);

		SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFFFFF);

	}

}
@@ -1113,15 +1111,15 @@ static int vcn_v1_0_start(struct amdgpu_device *adev) 
 */

static int vcn_v1_0_stop_spg_mode(struct amdgpu_device *adev)

{

	int ret_code, tmp;

	int tmp;



	SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, ret_code);

	SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7);



	tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |

		UVD_LMI_STATUS__READ_CLEAN_MASK |

		UVD_LMI_STATUS__WRITE_CLEAN_MASK |

		UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;

	SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp, ret_code);

	SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp);



	/* put VCPU into reset */

	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
@@ -1130,7 +1128,7 @@ static int vcn_v1_0_stop_spg_mode(struct amdgpu_device *adev) 


	tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |

		UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;

	SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp, ret_code);

	SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp);



	/* disable VCPU clock */

	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0,
@@ -1154,30 +1152,29 @@ static int vcn_v1_0_stop_spg_mode(struct amdgpu_device *adev) 


static int vcn_v1_0_stop_dpg_mode(struct amdgpu_device *adev)

{

	int ret_code = 0;

	uint32_t tmp;



	/* Wait for power status to be UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF */

	SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,

			UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,

			UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);

			UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);



	/* wait for read ptr to be equal to write ptr */

	tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);

	SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);

	SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF);



	tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);

	SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF, ret_code);

	SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF);



	tmp = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);

	SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_JRBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);

	SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_JRBC_RB_RPTR, tmp, 0xFFFFFFFF);



	tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;

	SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);

	SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF);



	SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,

		UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,

		UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);

		UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);



	/* disable dynamic power gating mode */

	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,
@@ -1220,9 +1217,9 @@ static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev, 
			ret_code = 0;



			if (!(reg_data & UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK))

				SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,

				ret_code = SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,

						   UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,

						   UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);

						   UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);



			if (!ret_code) {

				/* pause DPG non-jpeg */
@@ -1230,7 +1227,7 @@ static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev, 
				WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);

				SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE,

						   UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,

						   UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, ret_code);

						   UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);



				/* Restore */

				ring = &adev->vcn.inst->ring_enc[0];
@@ -1252,7 +1249,7 @@ static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev, 
						   RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF);

				SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,

						   UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON,

						   UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);

						   UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);

			}

		} else {

			/* unpause dpg non-jpeg, no need to wait */
@@ -1276,9 +1273,9 @@ static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev, 
			ret_code = 0;



			if (!(reg_data & UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK))

				SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,

				ret_code = SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,

						   UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,

						   UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);

						   UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);



			if (!ret_code) {

				/* Make sure JPRG Snoop is disabled before sending the pause */
@@ -1291,7 +1288,7 @@ static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev, 
				WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);

				SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE,

							UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK,

							UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK, ret_code);

							UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK);



				/* Restore */

				ring = &adev->jpeg.inst->ring_dec;
@@ -1313,7 +1310,7 @@ static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev, 
						   RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF);

				SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,

						   UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON,

						   UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);

						   UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);

			}

		} else {

			/* unpause dpg jpeg, no need to wait */
@@ -1336,10 +1333,10 @@ static bool vcn_v1_0_is_idle(void *handle) 
static int vcn_v1_0_wait_for_idle(void *handle)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	int ret = 0;

	int ret;



	SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE,

		UVD_STATUS__IDLE, ret);

	ret = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE,

		UVD_STATUS__IDLE);



	return ret;

}

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