Commit 44fb3026 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'tegra-for-4.2-emc' of... 

Merge tag 'tegra-for-4.2-emc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/drivers

Merge "ARM: tegra: Add EMC driver for v4.2-rc1" from Thierry Reding:

This introduces the EMC driver that's required to scale the external
memory frequency.

* tag 'tegra-for-4.2-emc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  memory: tegra: Add EMC frequency debugfs entry
  memory: tegra: Add EMC (external memory controller) driver
  memory: tegra: Add API needed by the EMC driver
  of: Add Tegra124 EMC bindings
  of: Document timings subnode of nvidia,tegra-mc
parents 92d19e26 9c77a81f

Documentation/devicetree/bindings/memory-controllers/nvidia,tegra-mc.txt

+82 −2
Original line number Diff line number Diff line 
NVIDIA Tegra Memory Controller device tree bindings

===================================================



memory-controller node

----------------------



Required properties:

- compatible: Should be "nvidia,tegra<chip>-mc"

- reg: Physical base address and length of the controller's registers.
@@ -15,9 +18,49 @@ Required properties: 
This device implements an IOMMU that complies with the generic IOMMU binding.

See ../iommu/iommu.txt for details.



Example:

--------

emc-timings subnode

-------------------



The node should contain a "emc-timings" subnode for each supported RAM type (see field RAM_CODE in

register PMC_STRAPPING_OPT_A).



Required properties for "emc-timings" nodes :

- nvidia,ram-code : Should contain the value of RAM_CODE this timing set is used for.



timing subnode

--------------



Each "emc-timings" node should contain a subnode for every supported EMC clock rate.



Required properties for timing nodes :

- clock-frequency : Should contain the memory clock rate in Hz.

- nvidia,emem-configuration : Values to be written to the EMEM register block. For the Tegra124 SoC

(see section "15.6.1 MC Registers" in the TRM), these are the registers whose values need to be

specified, according to the board documentation:



	MC_EMEM_ARB_CFG

	MC_EMEM_ARB_OUTSTANDING_REQ

	MC_EMEM_ARB_TIMING_RCD

	MC_EMEM_ARB_TIMING_RP

	MC_EMEM_ARB_TIMING_RC

	MC_EMEM_ARB_TIMING_RAS

	MC_EMEM_ARB_TIMING_FAW

	MC_EMEM_ARB_TIMING_RRD

	MC_EMEM_ARB_TIMING_RAP2PRE

	MC_EMEM_ARB_TIMING_WAP2PRE

	MC_EMEM_ARB_TIMING_R2R

	MC_EMEM_ARB_TIMING_W2W

	MC_EMEM_ARB_TIMING_R2W

	MC_EMEM_ARB_TIMING_W2R

	MC_EMEM_ARB_DA_TURNS

	MC_EMEM_ARB_DA_COVERS

	MC_EMEM_ARB_MISC0

	MC_EMEM_ARB_MISC1

	MC_EMEM_ARB_RING1_THROTTLE



Example SoC include file:



/ {

	mc: memory-controller@0,70019000 {

		compatible = "nvidia,tegra124-mc";

		reg = <0x0 0x70019000 0x0 0x1000>;
@@ -34,3 +77,40 @@ Example: 
		...

		iommus = <&mc TEGRA_SWGROUP_SDMMC1A>;

	};

};



Example board file:



/ {

	memory-controller@0,70019000 {

		emc-timings-3 {

			nvidia,ram-code = <3>;



			timing-12750000 {

				clock-frequency = <12750000>;



				nvidia,emem-configuration = <

					0x40040001 /* MC_EMEM_ARB_CFG */

					0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */

					0x00000001 /* MC_EMEM_ARB_TIMING_RCD */

					0x00000001 /* MC_EMEM_ARB_TIMING_RP */

					0x00000002 /* MC_EMEM_ARB_TIMING_RC */

					0x00000000 /* MC_EMEM_ARB_TIMING_RAS */

					0x00000002 /* MC_EMEM_ARB_TIMING_FAW */

					0x00000001 /* MC_EMEM_ARB_TIMING_RRD */

					0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */

					0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */

					0x00000003 /* MC_EMEM_ARB_TIMING_R2R */

					0x00000002 /* MC_EMEM_ARB_TIMING_W2W */

					0x00000003 /* MC_EMEM_ARB_TIMING_R2W */

					0x00000006 /* MC_EMEM_ARB_TIMING_W2R */

					0x06030203 /* MC_EMEM_ARB_DA_TURNS */

					0x000a0402 /* MC_EMEM_ARB_DA_COVERS */

					0x77e30303 /* MC_EMEM_ARB_MISC0 */

					0x70000f03 /* MC_EMEM_ARB_MISC1 */

					0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */

				>;

			};

		};

	};

};

Documentation/devicetree/bindings/memory-controllers/tegra-emc.txt

0 → 100644
+374 −0
Original line number Diff line number Diff line 
NVIDIA Tegra124 SoC EMC (external memory controller)

====================================================



Required properties :

- compatible : Should be "nvidia,tegra124-emc".

- reg : physical base address and length of the controller's registers.

- nvidia,memory-controller : phandle of the MC driver.



The node should contain a "emc-timings" subnode for each supported RAM type

(see field RAM_CODE in register PMC_STRAPPING_OPT_A), with its unit address

being its RAM_CODE.



Required properties for "emc-timings" nodes :

- nvidia,ram-code : Should contain the value of RAM_CODE this timing set is

used for.



Each "emc-timings" node should contain a "timing" subnode for every supported

EMC clock rate. The "timing" subnodes should have the clock rate in Hz as

their unit address.



Required properties for "timing" nodes :

- clock-frequency : Should contain the memory clock rate in Hz.

- The following properties contain EMC timing characterization values

(specified in the board documentation) :

  - nvidia,emc-auto-cal-config : EMC_AUTO_CAL_CONFIG

  - nvidia,emc-auto-cal-config2 : EMC_AUTO_CAL_CONFIG2

  - nvidia,emc-auto-cal-config3 : EMC_AUTO_CAL_CONFIG3

  - nvidia,emc-auto-cal-interval : EMC_AUTO_CAL_INTERVAL

  - nvidia,emc-bgbias-ctl0 : EMC_BGBIAS_CTL0

  - nvidia,emc-cfg : EMC_CFG

  - nvidia,emc-cfg-2 : EMC_CFG_2

  - nvidia,emc-ctt-term-ctrl : EMC_CTT_TERM_CTRL

  - nvidia,emc-mode-1 : Mode Register 1

  - nvidia,emc-mode-2 : Mode Register 2

  - nvidia,emc-mode-4 : Mode Register 4

  - nvidia,emc-mode-reset : Mode Register 0

  - nvidia,emc-mrs-wait-cnt : EMC_MRS_WAIT_CNT

  - nvidia,emc-sel-dpd-ctrl : EMC_SEL_DPD_CTRL

  - nvidia,emc-xm2dqspadctrl2 : EMC_XM2DQSPADCTRL2

  - nvidia,emc-zcal-cnt-long : EMC_ZCAL_WAIT_CNT after clock change

  - nvidia,emc-zcal-interval : EMC_ZCAL_INTERVAL

- nvidia,emc-configuration : EMC timing characterization data. These are the

registers (see section "15.6.2 EMC Registers" in the TRM) whose values need to

be specified, according to the board documentation:



	EMC_RC

	EMC_RFC

	EMC_RFC_SLR

	EMC_RAS

	EMC_RP

	EMC_R2W

	EMC_W2R

	EMC_R2P

	EMC_W2P

	EMC_RD_RCD

	EMC_WR_RCD

	EMC_RRD

	EMC_REXT

	EMC_WEXT

	EMC_WDV

	EMC_WDV_MASK

	EMC_QUSE

	EMC_QUSE_WIDTH

	EMC_IBDLY

	EMC_EINPUT

	EMC_EINPUT_DURATION

	EMC_PUTERM_EXTRA

	EMC_PUTERM_WIDTH

	EMC_PUTERM_ADJ

	EMC_CDB_CNTL_1

	EMC_CDB_CNTL_2

	EMC_CDB_CNTL_3

	EMC_QRST

	EMC_QSAFE

	EMC_RDV

	EMC_RDV_MASK

	EMC_REFRESH

	EMC_BURST_REFRESH_NUM

	EMC_PRE_REFRESH_REQ_CNT

	EMC_PDEX2WR

	EMC_PDEX2RD

	EMC_PCHG2PDEN

	EMC_ACT2PDEN

	EMC_AR2PDEN

	EMC_RW2PDEN

	EMC_TXSR

	EMC_TXSRDLL

	EMC_TCKE

	EMC_TCKESR

	EMC_TPD

	EMC_TFAW

	EMC_TRPAB

	EMC_TCLKSTABLE

	EMC_TCLKSTOP

	EMC_TREFBW

	EMC_FBIO_CFG6

	EMC_ODT_WRITE

	EMC_ODT_READ

	EMC_FBIO_CFG5

	EMC_CFG_DIG_DLL

	EMC_CFG_DIG_DLL_PERIOD

	EMC_DLL_XFORM_DQS0

	EMC_DLL_XFORM_DQS1

	EMC_DLL_XFORM_DQS2

	EMC_DLL_XFORM_DQS3

	EMC_DLL_XFORM_DQS4

	EMC_DLL_XFORM_DQS5

	EMC_DLL_XFORM_DQS6

	EMC_DLL_XFORM_DQS7

	EMC_DLL_XFORM_DQS8

	EMC_DLL_XFORM_DQS9

	EMC_DLL_XFORM_DQS10

	EMC_DLL_XFORM_DQS11

	EMC_DLL_XFORM_DQS12

	EMC_DLL_XFORM_DQS13

	EMC_DLL_XFORM_DQS14

	EMC_DLL_XFORM_DQS15

	EMC_DLL_XFORM_QUSE0

	EMC_DLL_XFORM_QUSE1

	EMC_DLL_XFORM_QUSE2

	EMC_DLL_XFORM_QUSE3

	EMC_DLL_XFORM_QUSE4

	EMC_DLL_XFORM_QUSE5

	EMC_DLL_XFORM_QUSE6

	EMC_DLL_XFORM_QUSE7

	EMC_DLL_XFORM_ADDR0

	EMC_DLL_XFORM_ADDR1

	EMC_DLL_XFORM_ADDR2

	EMC_DLL_XFORM_ADDR3

	EMC_DLL_XFORM_ADDR4

	EMC_DLL_XFORM_ADDR5

	EMC_DLL_XFORM_QUSE8

	EMC_DLL_XFORM_QUSE9

	EMC_DLL_XFORM_QUSE10

	EMC_DLL_XFORM_QUSE11

	EMC_DLL_XFORM_QUSE12

	EMC_DLL_XFORM_QUSE13

	EMC_DLL_XFORM_QUSE14

	EMC_DLL_XFORM_QUSE15

	EMC_DLI_TRIM_TXDQS0

	EMC_DLI_TRIM_TXDQS1

	EMC_DLI_TRIM_TXDQS2

	EMC_DLI_TRIM_TXDQS3

	EMC_DLI_TRIM_TXDQS4

	EMC_DLI_TRIM_TXDQS5

	EMC_DLI_TRIM_TXDQS6

	EMC_DLI_TRIM_TXDQS7

	EMC_DLI_TRIM_TXDQS8

	EMC_DLI_TRIM_TXDQS9

	EMC_DLI_TRIM_TXDQS10

	EMC_DLI_TRIM_TXDQS11

	EMC_DLI_TRIM_TXDQS12

	EMC_DLI_TRIM_TXDQS13

	EMC_DLI_TRIM_TXDQS14

	EMC_DLI_TRIM_TXDQS15

	EMC_DLL_XFORM_DQ0

	EMC_DLL_XFORM_DQ1

	EMC_DLL_XFORM_DQ2

	EMC_DLL_XFORM_DQ3

	EMC_DLL_XFORM_DQ4

	EMC_DLL_XFORM_DQ5

	EMC_DLL_XFORM_DQ6

	EMC_DLL_XFORM_DQ7

	EMC_XM2CMDPADCTRL

	EMC_XM2CMDPADCTRL4

	EMC_XM2CMDPADCTRL5

	EMC_XM2DQPADCTRL2

	EMC_XM2DQPADCTRL3

	EMC_XM2CLKPADCTRL

	EMC_XM2CLKPADCTRL2

	EMC_XM2COMPPADCTRL

	EMC_XM2VTTGENPADCTRL

	EMC_XM2VTTGENPADCTRL2

	EMC_XM2VTTGENPADCTRL3

	EMC_XM2DQSPADCTRL3

	EMC_XM2DQSPADCTRL4

	EMC_XM2DQSPADCTRL5

	EMC_XM2DQSPADCTRL6

	EMC_DSR_VTTGEN_DRV

	EMC_TXDSRVTTGEN

	EMC_FBIO_SPARE

	EMC_ZCAL_WAIT_CNT

	EMC_MRS_WAIT_CNT2

	EMC_CTT

	EMC_CTT_DURATION

	EMC_CFG_PIPE

	EMC_DYN_SELF_REF_CONTROL

	EMC_QPOP



Example SoC include file:



/ {

	emc@0,7001b000 {

		compatible = "nvidia,tegra124-emc";

		reg = <0x0 0x7001b000 0x0 0x1000>;



		nvidia,memory-controller = <&mc>;

	};

};



Example board file:



/ {

	emc@0,7001b000 {

		emc-timings-3 {

			nvidia,ram-code = <3>;



			timing-12750000 {

				clock-frequency = <12750000>;



				nvidia,emc-zcal-cnt-long = <0x00000042>;

				nvidia,emc-auto-cal-interval = <0x001fffff>;

				nvidia,emc-ctt-term-ctrl = <0x00000802>;

				nvidia,emc-cfg = <0x73240000>;

				nvidia,emc-cfg-2 = <0x000008c5>;

				nvidia,emc-sel-dpd-ctrl = <0x00040128>;

				nvidia,emc-bgbias-ctl0 = <0x00000008>;

				nvidia,emc-auto-cal-config = <0xa1430000>;

				nvidia,emc-auto-cal-config2 = <0x00000000>;

				nvidia,emc-auto-cal-config3 = <0x00000000>;

				nvidia,emc-mode-reset = <0x80001221>;

				nvidia,emc-mode-1 = <0x80100003>;

				nvidia,emc-mode-2 = <0x80200008>;

				nvidia,emc-mode-4 = <0x00000000>;



				nvidia,emc-configuration = <

					0x00000000 /* EMC_RC */

					0x00000003 /* EMC_RFC */

					0x00000000 /* EMC_RFC_SLR */

					0x00000000 /* EMC_RAS */

					0x00000000 /* EMC_RP */

					0x00000004 /* EMC_R2W */

					0x0000000a /* EMC_W2R */

					0x00000003 /* EMC_R2P */

					0x0000000b /* EMC_W2P */

					0x00000000 /* EMC_RD_RCD */

					0x00000000 /* EMC_WR_RCD */

					0x00000003 /* EMC_RRD */

					0x00000003 /* EMC_REXT */

					0x00000000 /* EMC_WEXT */

					0x00000006 /* EMC_WDV */

					0x00000006 /* EMC_WDV_MASK */

					0x00000006 /* EMC_QUSE */

					0x00000002 /* EMC_QUSE_WIDTH */

					0x00000000 /* EMC_IBDLY */

					0x00000005 /* EMC_EINPUT */

					0x00000005 /* EMC_EINPUT_DURATION */

					0x00010000 /* EMC_PUTERM_EXTRA */

					0x00000003 /* EMC_PUTERM_WIDTH */

					0x00000000 /* EMC_PUTERM_ADJ */

					0x00000000 /* EMC_CDB_CNTL_1 */

					0x00000000 /* EMC_CDB_CNTL_2 */

					0x00000000 /* EMC_CDB_CNTL_3 */

					0x00000004 /* EMC_QRST */

					0x0000000c /* EMC_QSAFE */

					0x0000000d /* EMC_RDV */

					0x0000000f /* EMC_RDV_MASK */

					0x00000060 /* EMC_REFRESH */

					0x00000000 /* EMC_BURST_REFRESH_NUM */

					0x00000018 /* EMC_PRE_REFRESH_REQ_CNT */

					0x00000002 /* EMC_PDEX2WR */

					0x00000002 /* EMC_PDEX2RD */

					0x00000001 /* EMC_PCHG2PDEN */

					0x00000000 /* EMC_ACT2PDEN */

					0x00000007 /* EMC_AR2PDEN */

					0x0000000f /* EMC_RW2PDEN */

					0x00000005 /* EMC_TXSR */

					0x00000005 /* EMC_TXSRDLL */

					0x00000004 /* EMC_TCKE */

					0x00000005 /* EMC_TCKESR */

					0x00000004 /* EMC_TPD */

					0x00000000 /* EMC_TFAW */

					0x00000000 /* EMC_TRPAB */

					0x00000005 /* EMC_TCLKSTABLE */

					0x00000005 /* EMC_TCLKSTOP */

					0x00000064 /* EMC_TREFBW */

					0x00000000 /* EMC_FBIO_CFG6 */

					0x00000000 /* EMC_ODT_WRITE */

					0x00000000 /* EMC_ODT_READ */

					0x106aa298 /* EMC_FBIO_CFG5 */

					0x002c00a0 /* EMC_CFG_DIG_DLL */

					0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */

					0x00064000 /* EMC_DLL_XFORM_DQS0 */

					0x00064000 /* EMC_DLL_XFORM_DQS1 */

					0x00064000 /* EMC_DLL_XFORM_DQS2 */

					0x00064000 /* EMC_DLL_XFORM_DQS3 */

					0x00064000 /* EMC_DLL_XFORM_DQS4 */

					0x00064000 /* EMC_DLL_XFORM_DQS5 */

					0x00064000 /* EMC_DLL_XFORM_DQS6 */

					0x00064000 /* EMC_DLL_XFORM_DQS7 */

					0x00064000 /* EMC_DLL_XFORM_DQS8 */

					0x00064000 /* EMC_DLL_XFORM_DQS9 */

					0x00064000 /* EMC_DLL_XFORM_DQS10 */

					0x00064000 /* EMC_DLL_XFORM_DQS11 */

					0x00064000 /* EMC_DLL_XFORM_DQS12 */

					0x00064000 /* EMC_DLL_XFORM_DQS13 */

					0x00064000 /* EMC_DLL_XFORM_DQS14 */

					0x00064000 /* EMC_DLL_XFORM_DQS15 */

					0x00000000 /* EMC_DLL_XFORM_QUSE0 */

					0x00000000 /* EMC_DLL_XFORM_QUSE1 */

					0x00000000 /* EMC_DLL_XFORM_QUSE2 */

					0x00000000 /* EMC_DLL_XFORM_QUSE3 */

					0x00000000 /* EMC_DLL_XFORM_QUSE4 */

					0x00000000 /* EMC_DLL_XFORM_QUSE5 */

					0x00000000 /* EMC_DLL_XFORM_QUSE6 */

					0x00000000 /* EMC_DLL_XFORM_QUSE7 */

					0x00000000 /* EMC_DLL_XFORM_ADDR0 */

					0x00000000 /* EMC_DLL_XFORM_ADDR1 */

					0x00000000 /* EMC_DLL_XFORM_ADDR2 */

					0x00000000 /* EMC_DLL_XFORM_ADDR3 */

					0x00000000 /* EMC_DLL_XFORM_ADDR4 */

					0x00000000 /* EMC_DLL_XFORM_ADDR5 */

					0x00000000 /* EMC_DLL_XFORM_QUSE8 */

					0x00000000 /* EMC_DLL_XFORM_QUSE9 */

					0x00000000 /* EMC_DLL_XFORM_QUSE10 */

					0x00000000 /* EMC_DLL_XFORM_QUSE11 */

					0x00000000 /* EMC_DLL_XFORM_QUSE12 */

					0x00000000 /* EMC_DLL_XFORM_QUSE13 */

					0x00000000 /* EMC_DLL_XFORM_QUSE14 */

					0x00000000 /* EMC_DLL_XFORM_QUSE15 */

					0x00000000 /* EMC_DLI_TRIM_TXDQS0 */

					0x00000000 /* EMC_DLI_TRIM_TXDQS1 */

					0x00000000 /* EMC_DLI_TRIM_TXDQS2 */

					0x00000000 /* EMC_DLI_TRIM_TXDQS3 */

					0x00000000 /* EMC_DLI_TRIM_TXDQS4 */

					0x00000000 /* EMC_DLI_TRIM_TXDQS5 */

					0x00000000 /* EMC_DLI_TRIM_TXDQS6 */

					0x00000000 /* EMC_DLI_TRIM_TXDQS7 */

					0x00000000 /* EMC_DLI_TRIM_TXDQS8 */

					0x00000000 /* EMC_DLI_TRIM_TXDQS9 */

					0x00000000 /* EMC_DLI_TRIM_TXDQS10 */

					0x00000000 /* EMC_DLI_TRIM_TXDQS11 */

					0x00000000 /* EMC_DLI_TRIM_TXDQS12 */

					0x00000000 /* EMC_DLI_TRIM_TXDQS13 */

					0x00000000 /* EMC_DLI_TRIM_TXDQS14 */

					0x00000000 /* EMC_DLI_TRIM_TXDQS15 */

					0x000fc000 /* EMC_DLL_XFORM_DQ0 */

					0x000fc000 /* EMC_DLL_XFORM_DQ1 */

					0x000fc000 /* EMC_DLL_XFORM_DQ2 */

					0x000fc000 /* EMC_DLL_XFORM_DQ3 */

					0x0000fc00 /* EMC_DLL_XFORM_DQ4 */

					0x0000fc00 /* EMC_DLL_XFORM_DQ5 */

					0x0000fc00 /* EMC_DLL_XFORM_DQ6 */

					0x0000fc00 /* EMC_DLL_XFORM_DQ7 */

					0x10000280 /* EMC_XM2CMDPADCTRL */

					0x00000000 /* EMC_XM2CMDPADCTRL4 */

					0x00111111 /* EMC_XM2CMDPADCTRL5 */

					0x00000000 /* EMC_XM2DQPADCTRL2 */

					0x00000000 /* EMC_XM2DQPADCTRL3 */

					0x77ffc081 /* EMC_XM2CLKPADCTRL */

					0x00000e0e /* EMC_XM2CLKPADCTRL2 */

					0x81f1f108 /* EMC_XM2COMPPADCTRL */

					0x07070004 /* EMC_XM2VTTGENPADCTRL */

					0x0000003f /* EMC_XM2VTTGENPADCTRL2 */

					0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */

					0x51451400 /* EMC_XM2DQSPADCTRL3 */

					0x00514514 /* EMC_XM2DQSPADCTRL4 */

					0x00514514 /* EMC_XM2DQSPADCTRL5 */

					0x51451400 /* EMC_XM2DQSPADCTRL6 */

					0x0000003f /* EMC_DSR_VTTGEN_DRV */

					0x00000007 /* EMC_TXDSRVTTGEN */

					0x00000000 /* EMC_FBIO_SPARE */

					0x00000042 /* EMC_ZCAL_WAIT_CNT */

					0x000e000e /* EMC_MRS_WAIT_CNT2 */

					0x00000000 /* EMC_CTT */

					0x00000003 /* EMC_CTT_DURATION */

					0x0000f2f3 /* EMC_CFG_PIPE */

					0x800001c5 /* EMC_DYN_SELF_REF_CONTROL */

					0x0000000a /* EMC_QPOP */

				>;

			};

		};

	};

};

drivers/memory/tegra/Kconfig

+10 −0
Original line number Diff line number Diff line
@@ -5,3 +5,13 @@ config TEGRA_MC 
	help

	  This driver supports the Memory Controller (MC) hardware found on

	  NVIDIA Tegra SoCs.



config TEGRA124_EMC

	bool "NVIDIA Tegra124 External Memory Controller driver"

	default y

	depends on TEGRA_MC && ARCH_TEGRA_124_SOC

	help

	  This driver is for the External Memory Controller (EMC) found on

	  Tegra124 chips. The EMC controls the external DRAM on the board.

	  This driver is required to change memory timings / clock rate for

	  external memory.

drivers/memory/tegra/Makefile

+2 −0
Original line number Diff line number Diff line
@@ -6,3 +6,5 @@ tegra-mc-$(CONFIG_ARCH_TEGRA_124_SOC) += tegra124.o 
tegra-mc-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra124.o



obj-$(CONFIG_TEGRA_MC) += tegra-mc.o



obj-$(CONFIG_TEGRA124_EMC) += tegra124-emc.o

drivers/memory/tegra/mc.c

+136 −0
Original line number Diff line number Diff line
@@ -13,6 +13,9 @@ 
#include <linux/of.h>

#include <linux/platform_device.h>

#include <linux/slab.h>

#include <linux/sort.h>



#include <soc/tegra/fuse.h>



#include "mc.h"
@@ -48,6 +51,9 @@ 
#define  MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK	0x1ff

#define MC_EMEM_ARB_MISC0 0xd8



#define MC_EMEM_ADR_CFG 0x54

#define MC_EMEM_ADR_CFG_EMEM_NUMDEV BIT(0)



static const struct of_device_id tegra_mc_of_match[] = {

#ifdef CONFIG_ARCH_TEGRA_3x_SOC

	{ .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc },
@@ -94,6 +100,130 @@ static int tegra_mc_setup_latency_allowance(struct tegra_mc *mc) 
	return 0;

}



void tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate)

{

	unsigned int i;

	struct tegra_mc_timing *timing = NULL;



	for (i = 0; i < mc->num_timings; i++) {

		if (mc->timings[i].rate == rate) {

			timing = &mc->timings[i];

			break;

		}

	}



	if (!timing) {

		dev_err(mc->dev, "no memory timing registered for rate %lu\n",

			rate);

		return;

	}



	for (i = 0; i < mc->soc->num_emem_regs; ++i)

		mc_writel(mc, timing->emem_data[i], mc->soc->emem_regs[i]);

}



unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc)

{

	u8 dram_count;



	dram_count = mc_readl(mc, MC_EMEM_ADR_CFG);

	dram_count &= MC_EMEM_ADR_CFG_EMEM_NUMDEV;

	dram_count++;



	return dram_count;

}



static int load_one_timing(struct tegra_mc *mc,

			   struct tegra_mc_timing *timing,

			   struct device_node *node)

{

	int err;

	u32 tmp;



	err = of_property_read_u32(node, "clock-frequency", &tmp);

	if (err) {

		dev_err(mc->dev,

			"timing %s: failed to read rate\n", node->name);

		return err;

	}



	timing->rate = tmp;

	timing->emem_data = devm_kcalloc(mc->dev, mc->soc->num_emem_regs,

					 sizeof(u32), GFP_KERNEL);

	if (!timing->emem_data)

		return -ENOMEM;



	err = of_property_read_u32_array(node, "nvidia,emem-configuration",

					 timing->emem_data,

					 mc->soc->num_emem_regs);

	if (err) {

		dev_err(mc->dev,

			"timing %s: failed to read EMEM configuration\n",

			node->name);

		return err;

	}



	return 0;

}



static int load_timings(struct tegra_mc *mc, struct device_node *node)

{

	struct device_node *child;

	struct tegra_mc_timing *timing;

	int child_count = of_get_child_count(node);

	int i = 0, err;



	mc->timings = devm_kcalloc(mc->dev, child_count, sizeof(*timing),

				   GFP_KERNEL);

	if (!mc->timings)

		return -ENOMEM;



	mc->num_timings = child_count;



	for_each_child_of_node(node, child) {

		timing = &mc->timings[i++];



		err = load_one_timing(mc, timing, child);

		if (err)

			return err;

	}



	return 0;

}



static int tegra_mc_setup_timings(struct tegra_mc *mc)

{

	struct device_node *node;

	u32 ram_code, node_ram_code;

	int err;



	ram_code = tegra_read_ram_code();



	mc->num_timings = 0;



	for_each_child_of_node(mc->dev->of_node, node) {

		err = of_property_read_u32(node, "nvidia,ram-code",

					   &node_ram_code);

		if (err || (node_ram_code != ram_code)) {

			of_node_put(node);

			continue;

		}



		err = load_timings(mc, node);

		if (err)

			return err;

		of_node_put(node);

		break;

	}



	if (mc->num_timings == 0)

		dev_warn(mc->dev,

			 "no memory timings for RAM code %u registered\n",

			 ram_code);



	return 0;

}



static const char *const status_names[32] = {

	[ 1] = "External interrupt",

	[ 6] = "EMEM address decode error",
@@ -251,6 +381,12 @@ static int tegra_mc_probe(struct platform_device *pdev) 
		return err;

	}



	err = tegra_mc_setup_timings(mc);

	if (err < 0) {

		dev_err(&pdev->dev, "failed to setup timings: %d\n", err);

		return err;

	}



	if (IS_ENABLED(CONFIG_TEGRA_IOMMU_SMMU)) {

		mc->smmu = tegra_smmu_probe(&pdev->dev, mc->soc->smmu, mc);

		if (IS_ERR(mc->smmu)) {

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