Commit 44e1baeb authored by Christian König's avatar Christian König Committed by Alex Deucher
Browse files

drm/amdgpu: revert "Add support for filling a buffer with 64 bit value" 



This reverts commit 7bdc53f9 and commit
330df03b.

Neither are needed any more.

Signed-off-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarFelix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 8febe617

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+0 −7
Original line number Diff line number Diff line
@@ -319,13 +319,6 @@ struct amdgpu_vm_pte_funcs { 
	void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe,

			  uint64_t value, unsigned count,

			  uint32_t incr);



	/* maximum nums of PTEs/PDEs in a single operation */

	uint32_t	set_max_nums_pte_pde;



	/* number of dw to reserve per operation */

	unsigned	set_pte_pde_num_dw;



	/* for linear pte/pde updates without addr mapping */

	void (*set_pte_pde)(struct amdgpu_ib *ib,

			    uint64_t pe,

drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

+5 −12
Original line number Diff line number Diff line
@@ -1681,13 +1681,12 @@ error_free: 
}



int amdgpu_fill_buffer(struct amdgpu_bo *bo,

		       uint64_t src_data,

		       uint32_t src_data,

		       struct reservation_object *resv,

		       struct dma_fence **fence)

{

	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);

	uint32_t max_bytes = 8 *

			adev->vm_manager.vm_pte_funcs->set_max_nums_pte_pde;

	uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;

	struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;



	struct drm_mm_node *mm_node;
@@ -1718,9 +1717,7 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo, 
		num_pages -= mm_node->size;

		++mm_node;

	}



	/* num of dwords for each SDMA_OP_PTEPDE cmd */

	num_dw = num_loops * adev->vm_manager.vm_pte_funcs->set_pte_pde_num_dw;

	num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;



	/* for IB padding */

	num_dw += 64;
@@ -1745,16 +1742,12 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo, 
		uint32_t byte_count = mm_node->size << PAGE_SHIFT;

		uint64_t dst_addr;



		WARN_ONCE(byte_count & 0x7, "size should be a multiple of 8");



		dst_addr = amdgpu_mm_node_addr(&bo->tbo, mm_node, &bo->tbo.mem);

		while (byte_count) {

			uint32_t cur_size_in_bytes = min(byte_count, max_bytes);



			amdgpu_vm_set_pte_pde(adev, &job->ibs[0],

					dst_addr, 0,

					cur_size_in_bytes >> 3, 0,

					src_data);

			amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data,

						dst_addr, cur_size_in_bytes);



			dst_addr += cur_size_in_bytes;

			byte_count -= cur_size_in_bytes;

drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h

+1 −1
Original line number Diff line number Diff line
@@ -86,7 +86,7 @@ int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev, 
			       struct reservation_object *resv,

			       struct dma_fence **f);

int amdgpu_fill_buffer(struct amdgpu_bo *bo,

			uint64_t src_data,

			uint32_t src_data,

			struct reservation_object *resv,

			struct dma_fence **fence);

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c

+2 −3
Original line number Diff line number Diff line
@@ -1242,11 +1242,10 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, 


	} else {

		/* set page commands needed */

		ndw += ncmds * adev->vm_manager.vm_pte_funcs->set_pte_pde_num_dw;

		ndw += ncmds * 10;



		/* extra commands for begin/end fragments */

		ndw += 2 * adev->vm_manager.vm_pte_funcs->set_pte_pde_num_dw

				* adev->vm_manager.fragment_size;

		ndw += 2 * 10 * adev->vm_manager.fragment_size;



		params.func = amdgpu_vm_do_set_ptes;

	}

drivers/gpu/drm/amd/amdgpu/cik_sdma.c

+0 −3
Original line number Diff line number Diff line
@@ -1382,9 +1382,6 @@ static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs = { 
	.copy_pte = cik_sdma_vm_copy_pte,



	.write_pte = cik_sdma_vm_write_pte,



	.set_max_nums_pte_pde = 0x1fffff >> 3,

	.set_pte_pde_num_dw = 10,

	.set_pte_pde = cik_sdma_vm_set_pte_pde,

};

CRA Git | Maintained and supported by SUSTech CRA and CCSE