Commit 44c94100 authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files

Merge 4.20-rc5 into usb-next



We need the USB fixes into usb-next.

Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parents 77df6d8d 25956467
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+60 −3
Original line number Diff line number Diff line
@@ -856,7 +856,8 @@
			causing system reset or hang due to sending
			INIT from AP to BSP.

	disable_counter_freezing [HW]
	perf_v4_pmi=	[X86,INTEL]
			Format: <bool>
			Disable Intel PMU counter freezing feature.
			The feature only exists starting from
			Arch Perfmon v4 (Skylake and newer).
@@ -3504,6 +3505,10 @@
			before loading.
			See Documentation/blockdev/ramdisk.txt.

	psi=		[KNL] Enable or disable pressure stall information
			tracking.
			Format: <bool>

	psmouse.proto=	[HW,MOUSE] Highest PS2 mouse protocol extension to
			probe for; one of (bare|imps|exps|lifebook|any).
	psmouse.rate=	[HW,MOUSE] Set desired mouse report rate, in reports
@@ -4194,9 +4199,13 @@

	spectre_v2=	[X86] Control mitigation of Spectre variant 2
			(indirect branch speculation) vulnerability.
			The default operation protects the kernel from
			user space attacks.

			on   - unconditionally enable
			off  - unconditionally disable
			on   - unconditionally enable, implies
			       spectre_v2_user=on
			off  - unconditionally disable, implies
			       spectre_v2_user=off
			auto - kernel detects whether your CPU model is
			       vulnerable

@@ -4206,6 +4215,12 @@
			CONFIG_RETPOLINE configuration option, and the
			compiler with which the kernel was built.

			Selecting 'on' will also enable the mitigation
			against user space to user space task attacks.

			Selecting 'off' will disable both the kernel and
			the user space protections.

			Specific mitigations can also be selected manually:

			retpoline	  - replace indirect branches
@@ -4215,6 +4230,48 @@
			Not specifying this option is equivalent to
			spectre_v2=auto.

	spectre_v2_user=
			[X86] Control mitigation of Spectre variant 2
		        (indirect branch speculation) vulnerability between
		        user space tasks

			on	- Unconditionally enable mitigations. Is
				  enforced by spectre_v2=on

			off     - Unconditionally disable mitigations. Is
				  enforced by spectre_v2=off

			prctl   - Indirect branch speculation is enabled,
				  but mitigation can be enabled via prctl
				  per thread.  The mitigation control state
				  is inherited on fork.

			prctl,ibpb
				- Like "prctl" above, but only STIBP is
				  controlled per thread. IBPB is issued
				  always when switching between different user
				  space processes.

			seccomp
				- Same as "prctl" above, but all seccomp
				  threads will enable the mitigation unless
				  they explicitly opt out.

			seccomp,ibpb
				- Like "seccomp" above, but only STIBP is
				  controlled per thread. IBPB is issued
				  always when switching between different
				  user space processes.

			auto    - Kernel selects the mitigation depending on
				  the available CPU features and vulnerability.

			Default mitigation:
			If CONFIG_SECCOMP=y then "seccomp", otherwise "prctl"

			Not specifying this option is equivalent to
			spectre_v2_user=auto.

	spec_store_bypass_disable=
			[HW] Control Speculative Store Bypass (SSB) Disable mitigation
			(Speculative Store Bypass vulnerability)
+1 −0
Original line number Diff line number Diff line
@@ -57,6 +57,7 @@ stable kernels.
| ARM            | Cortex-A73      | #858921         | ARM64_ERRATUM_858921        |
| ARM            | Cortex-A55      | #1024718        | ARM64_ERRATUM_1024718       |
| ARM            | Cortex-A76      | #1188873        | ARM64_ERRATUM_1188873       |
| ARM            | Cortex-A76      | #1286807        | ARM64_ERRATUM_1286807       |
| ARM            | MMU-500         | #841119,#826419 | N/A                         |
|                |                 |                 |                             |
| Cavium         | ThunderX ITS    | #22375, #24313  | CAVIUM_ERRATUM_22375        |
+23 −8
Original line number Diff line number Diff line
@@ -40,24 +40,36 @@ Required properties:
		"ref" for 19.2 MHz ref clk,
		"com_aux" for phy common block aux clock,
		"ref_aux" for phy reference aux clock,

		For "qcom,ipq8074-qmp-pcie-phy": no clocks are listed.
		For "qcom,msm8996-qmp-pcie-phy" must contain:
			"aux", "cfg_ahb", "ref".
		For "qcom,msm8996-qmp-usb3-phy" must contain:
			"aux", "cfg_ahb", "ref".
		For "qcom,qmp-v3-usb3-phy" must contain:
		For "qcom,sdm845-qmp-usb3-phy" must contain:
			"aux", "cfg_ahb", "ref", "com_aux".
		For "qcom,sdm845-qmp-usb3-uni-phy" must contain:
			"aux", "cfg_ahb", "ref", "com_aux".
		For "qcom,sdm845-qmp-ufs-phy" must contain:
			"ref", "ref_aux".

 - resets: a list of phandles and reset controller specifier pairs,
	   one for each entry in reset-names.
 - reset-names: "phy" for reset of phy block,
		"common" for phy common block reset,
		"cfg" for phy's ahb cfg block reset (Optional).
		"cfg" for phy's ahb cfg block reset.

		For "qcom,ipq8074-qmp-pcie-phy" must contain:
			"phy", "common".
		For "qcom,msm8996-qmp-pcie-phy" must contain:
			"phy", "common", "cfg".
		For "qcom,msm8996-qmp-usb3-phy" must contain
			"phy", "common".
		For "qcom,ipq8074-qmp-pcie-phy" must contain:
		For "qcom,sdm845-qmp-usb3-phy" must contain:
			"phy", "common".
		For "qcom,sdm845-qmp-usb3-uni-phy" must contain:
			"phy", "common".
		For "qcom,sdm845-qmp-ufs-phy": no resets are listed.

 - vdda-phy-supply: Phandle to a regulator supply to PHY core block.
 - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.
@@ -79,9 +91,10 @@ Required properties for child node:

 - #phy-cells: must be 0

Required properties child node of pcie and usb3 qmp phys:
 - clocks: a list of phandles and clock-specifier pairs,
	   one for each entry in clock-names.
 - clock-names: Must contain following for pcie and usb qmp phys:
 - clock-names: Must contain following:
		 "pipe<lane-number>" for pipe clock specific to each lane.
 - clock-output-names: Name of the PHY clock that will be the parent for
		       the above pipe clock.
@@ -91,9 +104,11 @@ Required properties for child node:
			(or)
		  "pcie20_phy1_pipe_clk"

Required properties for child node of PHYs with lane reset, AKA:
	"qcom,msm8996-qmp-pcie-phy"
 - resets: a list of phandles and reset controller specifier pairs,
	   one for each entry in reset-names.
 - reset-names: Must contain following for pcie qmp phys:
 - reset-names: Must contain following:
		 "lane<lane-number>" for reset specific to each lane.

Example:
+8 −6
Original line number Diff line number Diff line
@@ -5,18 +5,20 @@ UniPhier SoCs have SCSSI which supports SPI single channel.
Required properties:
 - compatible: should be "socionext,uniphier-scssi"
 - reg: address and length of the spi master registers
 - #address-cells: must be <1>, see spi-bus.txt
 - #size-cells: must be <0>, see spi-bus.txt
 - clocks: A phandle to the clock for the device.
 - resets: A phandle to the reset control for the device.
 - interrupts: a single interrupt specifier
 - pinctrl-names: should be "default"
 - pinctrl-0: pin control state for the default mode
 - clocks: a phandle to the clock for the device
 - resets: a phandle to the reset control for the device

Example:

spi0: spi@54006000 {
	compatible = "socionext,uniphier-scssi";
	reg = <0x54006000 0x100>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <0 39 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_spi0>;
	clocks = <&peri_clk 11>;
	resets = <&peri_rst 11>;
};
+9 −0
Original line number Diff line number Diff line
@@ -92,3 +92,12 @@ Speculation misfeature controls
   * prctl(PR_SET_SPECULATION_CTRL, PR_SPEC_STORE_BYPASS, PR_SPEC_ENABLE, 0, 0);
   * prctl(PR_SET_SPECULATION_CTRL, PR_SPEC_STORE_BYPASS, PR_SPEC_DISABLE, 0, 0);
   * prctl(PR_SET_SPECULATION_CTRL, PR_SPEC_STORE_BYPASS, PR_SPEC_FORCE_DISABLE, 0, 0);

- PR_SPEC_INDIR_BRANCH: Indirect Branch Speculation in User Processes
                        (Mitigate Spectre V2 style attacks against user processes)

  Invocations:
   * prctl(PR_GET_SPECULATION_CTRL, PR_SPEC_INDIRECT_BRANCH, 0, 0, 0);
   * prctl(PR_SET_SPECULATION_CTRL, PR_SPEC_INDIRECT_BRANCH, PR_SPEC_ENABLE, 0, 0);
   * prctl(PR_SET_SPECULATION_CTRL, PR_SPEC_INDIRECT_BRANCH, PR_SPEC_DISABLE, 0, 0);
   * prctl(PR_SET_SPECULATION_CTRL, PR_SPEC_INDIRECT_BRANCH, PR_SPEC_FORCE_DISABLE, 0, 0);
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