Commit 44c916d5 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'cleanup-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc 

Pull ARM SoC cleanups from Olof Johansson:
 "This merge window brings a good size of cleanups on various platforms.
  Among the bigger ones:

   - Removal of Samsung s5pc100 and s5p64xx platforms.  Both of these
     have lacked active support for quite a while, and after asking
     around nobody showed interest in keeping them around.  If needed,
     they could be resurrected in the future but it's more likely that
     we would prefer reintroduction of them as DT and
     multiplatform-enabled platforms instead.

   - OMAP4 controller code register define diet.  They defined a lot of
     registers that were never actually used, etc.

   - Move of some of the Tegra platform code (PMC, APBIO, fuse,
     powergate) to drivers/soc so it can be shared with 64-bit code.
     This also converts them over to traditional driver models where
     possible.

   - Removal of legacy gpio-samsung driver, since the last users have
     been removed (moved to pinctrl)

  Plus a bunch of smaller changes for various platforms that sort of
  dissapear in the diffstat for the above.  clps711x cleanups, shmobile
  header file refactoring/moves for multiplatform friendliness, some
  misc cleanups, etc"

* tag 'cleanup-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (117 commits)
  drivers: CCI: Correct use of ! and &
  video: clcd-versatile: Depend on ARM
  video: fix up versatile CLCD helper move
  MAINTAINERS: Add sdhci-st file to ARCH/STI architecture
  ARM: EXYNOS: Fix build breakge with PM_SLEEP=n
  MAINTAINERS: Remove Kirkwood
  ARM: tegra: Convert PMC to a driver
  soc/tegra: fuse: Set up in early initcall
  ARM: tegra: Always lock the CPU reset vector
  ARM: tegra: Setup CPU hotplug in a pure initcall
  soc/tegra: Implement runtime check for Tegra SoCs
  soc/tegra: fuse: fix dummy functions
  soc/tegra: fuse: move APB DMA into Tegra20 fuse driver
  soc/tegra: Add efuse and apbmisc bindings
  soc/tegra: Add efuse driver for Tegra
  ARM: tegra: move fuse exports to soc/tegra/fuse.h
  ARM: tegra: export apb dma readl/writel
  ARM: tegra: Use a function to get the chip ID
  ARM: tegra: Sort includes alphabetically
  ARM: tegra: Move includes to include/soc/tegra
  ...
parents 889fa782 c4846a78

Documentation/ABI/testing/sysfs-driver-tegra-fuse

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What:		/sys/devices/*/<our-device>/fuse

Date:		February 2014

Contact:	Peter De Schrijver <pdeschrijver@nvidia.com>

Description:	read-only access to the efuses on Tegra20, Tegra30, Tegra114

		and Tegra124 SoC's from NVIDIA. The efuses contain write once

		data programmed at the factory. The data is layed out in 32bit

		words in LSB first format. Each bit represents a single value

		as decoded from the fuse registers. Bits order/assignment

		exactly matches the HW registers, including any unused bits.

Users:		any user space application which wants to read the efuses on

		Tegra SoC's

Documentation/arm/Samsung/Overview.txt

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@@ -13,8 +13,6 @@ Introduction 


  - S3C24XX: See Documentation/arm/Samsung-S3C24XX/Overview.txt for full list

  - S3C64XX: S3C6400 and S3C6410

  - S5P6440

  - S5PC100

  - S5PC110 / S5PV210
@@ -34,8 +32,6 @@ Configuration 
  A number of configurations are supplied, as there is no current way of

  unifying all the SoCs into one kernel.



  s5p6440_defconfig - S5P6440 specific default configuration

  s5pc100_defconfig - S5PC100 specific default configuration

  s5pc110_defconfig - S5PC110 specific default configuration

  s5pv210_defconfig - S5PV210 specific default configuration
@@ -67,13 +63,6 @@ Layout changes 
  where to simplify the include and dependency issues involved with having

  so many different platform directories.



  It was decided to remove plat-s5pc1xx as some of the support was already

  in plat-s5p or plat-samsung, with the S5PC110 support added with S5PV210

  the only user was the S5PC100. The S5PC100 specific items where moved to

  arch/arm/mach-s5pc100.









Port Contributors

-----------------

Documentation/arm/Samsung/clksrc-change-registers.awk

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@@ -68,7 +68,6 @@ BEGIN { 


    while (getline line < ARGV[1] > 0) {

	if (line ~ /\#define.*_MASK/ &&

	    !(line ~ /S5PC100_EPLL_MASK/) &&

	    !(line ~ /USB_SIG_MASK/)) {

	    splitdefine(line, fields)

	    name = fields[0]

Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt

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NVIDIA Tegra20/Tegra30/Tegr114/Tegra124 fuse block.



Required properties:

- compatible : should be:

	"nvidia,tegra20-efuse"

	"nvidia,tegra30-efuse"

	"nvidia,tegra114-efuse"

	"nvidia,tegra124-efuse"

  Details:

  nvidia,tegra20-efuse: Tegra20 requires using APB DMA to read the fuse data

	due to a hardware bug. Tegra20 also lacks certain information which is

	available in later generations such as fab code, lot code, wafer id,..

  nvidia,tegra30-efuse, nvidia,tegra114-efuse and nvidia,tegra124-efuse:

	The differences between these SoCs are the size of the efuse array,

	the location of the spare (OEM programmable) bits and the location of

	the speedo data.

- reg: Should contain 1 entry: the entry gives the physical address and length

       of the fuse registers.

- clocks: Must contain an entry for each entry in clock-names.

  See ../clocks/clock-bindings.txt for details.

- clock-names: Must include the following entries:

  - fuse

- resets: Must contain an entry for each entry in reset-names.

  See ../reset/reset.txt for details.

- reset-names: Must include the following entries:

 - fuse



Example:



	fuse@7000f800 {

		compatible = "nvidia,tegra20-efuse";

		reg = <0x7000F800 0x400>,

		      <0x70000000 0x400>;

		clocks = <&tegra_car TEGRA20_CLK_FUSE>;

		clock-names = "fuse";

		resets = <&tegra_car 39>;

		reset-names = "fuse";

	};

Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt

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NVIDIA Tegra20/Tegra30/Tegr114/Tegra124 apbmisc block



Required properties:

- compatible : should be:

       "nvidia,tegra20-apbmisc"

       "nvidia,tegra30-apbmisc"

       "nvidia,tegra114-apbmisc"

       "nvidia,tegra124-apbmisc"

- reg: Should contain 2 entries: the first entry gives the physical address

       and length of the registers which contain revision and debug features.

       The second entry gives the physical address and length of the

       registers indicating the strapping options.

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