Commit 44c10138 authored by Auke Kok's avatar Auke Kok Committed by Greg Kroah-Hartman
Browse files

PCI: Change all drivers to use pci_device->revision 



Instead of all drivers reading pci config space to get the revision
ID, they can now use the pci_device->revision member.

This exposes some issues where drivers where reading a word or a dword
for the revision number, and adding useless error-handling around the
read. Some drivers even just read it for no purpose of all.

In devices where the revision ID is being copied over and used in what
appears to be the equivalent of hotpath, I have left the copy code
and the cached copy as not to influence the driver's performance.

Compile tested with make all{yes,mod}config on x86_64 and i386.

Signed-off-by: default avatarAuke Kok <auke-jan.h.kok@intel.com>
Acked-by: default avatarDave Jones <davej@redhat.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
parent b8a3a521

arch/i386/kernel/cpu/cpufreq/cpufreq-nforce2.c

+1 −5
Original line number Diff line number Diff line
@@ -391,8 +391,6 @@ static struct cpufreq_driver nforce2_driver = { 
 */

static unsigned int nforce2_detect_chipset(void)

{

	u8 revision;



	nforce2_chipset_dev = pci_get_subsys(PCI_VENDOR_ID_NVIDIA,

					PCI_DEVICE_ID_NVIDIA_NFORCE2,

					PCI_ANY_ID, PCI_ANY_ID, NULL);
@@ -400,10 +398,8 @@ static unsigned int nforce2_detect_chipset(void) 
	if (nforce2_chipset_dev == NULL)

		return -ENODEV;



	pci_read_config_byte(nforce2_chipset_dev, PCI_REVISION_ID, &revision);



	printk(KERN_INFO "cpufreq: Detected nForce2 chipset revision %X\n",

	       revision);

	       nforce2_chipset_dev->revision);

	printk(KERN_INFO

	       "cpufreq: FSB changing is maybe unstable and can lead to crashes and data loss.\n");

arch/i386/kernel/cpu/cpufreq/gx-suspmod.c

+1 −3
Original line number Diff line number Diff line
@@ -115,7 +115,6 @@ struct gxfreq_params { 
	u8 pci_suscfg;

	u8 pci_pmer1;

	u8 pci_pmer2;

	u8 pci_rev;

	struct pci_dev *cs55x0;

};
@@ -276,7 +275,7 @@ static void gx_set_cpuspeed(unsigned int khz) 
			pci_write_config_byte(gx_params->cs55x0, PCI_VIDTC, 100);/* typical 50 to 100ms */

			pci_write_config_byte(gx_params->cs55x0, PCI_PMER1, pmer1);



			if (gx_params->pci_rev < 0x10) {   /* CS5530(rev 1.2, 1.3) */

			if (gx_params->cs55x0->revision < 0x10) {   /* CS5530(rev 1.2, 1.3) */

				suscfg = gx_params->pci_suscfg | SUSMOD;

			} else {                           /* CS5530A,B.. */

				suscfg = gx_params->pci_suscfg | SUSMOD | PWRSVE;
@@ -471,7 +470,6 @@ static int __init cpufreq_gx_init(void) 
	pci_read_config_byte(params->cs55x0, PCI_PMER2, &(params->pci_pmer2));

	pci_read_config_byte(params->cs55x0, PCI_MODON, &(params->on_duration));

	pci_read_config_byte(params->cs55x0, PCI_MODOFF, &(params->off_duration));

	pci_read_config_byte(params->cs55x0, PCI_REVISION_ID, &params->pci_rev);



	if ((ret = cpufreq_register_driver(&gx_suspmod_driver))) {

		kfree(params);

arch/i386/kernel/cpu/cpufreq/speedstep-ich.c

+1 −3
Original line number Diff line number Diff line
@@ -205,7 +205,6 @@ static unsigned int speedstep_detect_chipset (void) 
		 * host brige. Abort on these systems.

		 */

		static struct pci_dev *hostbridge;

		u8 rev = 0;



		hostbridge  = pci_get_subsys(PCI_VENDOR_ID_INTEL,

			      PCI_DEVICE_ID_INTEL_82815_MC,
@@ -216,8 +215,7 @@ static unsigned int speedstep_detect_chipset (void) 
		if (!hostbridge)

			return 2; /* 2-M */



		pci_read_config_byte(hostbridge, PCI_REVISION_ID, &rev);

		if (rev < 5) {

		if (hostbridge->revision < 5) {

			dprintk("hostbridge does not support speedstep\n");

			speedstep_chipset_dev = NULL;

			pci_dev_put(hostbridge);

arch/i386/pci/fixup.c

+3 −6
Original line number Diff line number Diff line
@@ -118,12 +118,9 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, pci 
static void pci_fixup_via_northbridge_bug(struct pci_dev *d)

{

	u8 v;

	u8 revision;

	int where = 0x55;

	int mask = 0x1f; /* clear bits 5, 6, 7 by default */



	pci_read_config_byte(d, PCI_REVISION_ID, &revision);



	if (d->device == PCI_DEVICE_ID_VIA_8367_0) {

		/* fix pci bus latency issues resulted by NB bios error

		   it appears on bug free^Wreduced kt266x's bios forces
@@ -133,8 +130,8 @@ static void pci_fixup_via_northbridge_bug(struct pci_dev *d) 
		where = 0x95; /* the memory write queue timer register is 

				different for the KT266x's: 0x95 not 0x55 */

	} else if (d->device == PCI_DEVICE_ID_VIA_8363_0 &&

			(revision == VIA_8363_KL133_REVISION_ID || 

			revision == VIA_8363_KM133_REVISION_ID)) {

			(d->revision == VIA_8363_KL133_REVISION_ID ||

			d->revision == VIA_8363_KM133_REVISION_ID)) {

			mask = 0x3f; /* clear only bits 6 and 7; clearing bit 5

					causes screen corruption on the KL133/KM133 */

	}
@@ -142,7 +139,7 @@ static void pci_fixup_via_northbridge_bug(struct pci_dev *d) 
	pci_read_config_byte(d, where, &v);

	if (v & ~mask) {

		printk(KERN_WARNING "Disabling VIA memory write queue (PCI ID %04x, rev %02x): [%02x] %02x & %02x -> %02x\n", \

			d->device, revision, where, v, mask, v & mask);

			d->device, d->revision, where, v, mask, v & mask);

		v &= mask;

		pci_write_config_byte(d, where, v);

	}

arch/mips/pci/fixup-cobalt.c

+3 −7
Original line number Diff line number Diff line
@@ -58,8 +58,6 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, 


static void qube_raq_galileo_fixup(struct pci_dev *dev)

{

	unsigned short galileo_id;



	if (dev->devfn != PCI_DEVFN(0, 0))

		return;
@@ -84,16 +82,14 @@ static void qube_raq_galileo_fixup(struct pci_dev *dev) 
	 * Therefore we must set the disconnect/retry cycle values to

	 * something sensible when using the new Galileo.

	 */

	pci_read_config_word(dev, PCI_REVISION_ID, &galileo_id);

	galileo_id &= 0xff;	/* mask off class info */



 	printk(KERN_INFO "Galileo: revision %u\n", galileo_id);

 	printk(KERN_INFO "Galileo: revision %u\n", dev->revision);



#if 0

	if (galileo_id >= 0x10) {

	if (dev->revision >= 0x10) {

		/* New Galileo, assumes PCI stop line to VIA is connected. */

		GT_WRITE(GT_PCI0_TOR_OFS, 0x4020);

	} else if (galileo_id == 0x1 || galileo_id == 0x2)

	} else if (dev->revision == 0x1 || dev->revision == 0x2)

#endif

	{

		signed int timeo;

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