Commit 44b3769b authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'RTL8125-EEE' 



Heiner Kallweit says:

====================
net: phy: realtek: support NBase-T MMD EEE registers on RTL8125

Add missing EEE-related constants, including the new MMD EEE registers
for NBase-T / 802.3bz. Based on that emulate the new 802.3bz MMD EEE
registers for 2.5Gbps EEE on RTL8125.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 607f625b edde25e5

drivers/net/phy/realtek.c

+43 −2
Original line number Diff line number Diff line
@@ -305,6 +305,47 @@ static int rtlgen_write_mmd(struct phy_device *phydev, int devnum, u16 regnum, 
	return ret;

}



static int rtl8125_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)

{

	int ret = rtlgen_read_mmd(phydev, devnum, regnum);



	if (ret != -EOPNOTSUPP)

		return ret;



	if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE2) {

		rtl821x_write_page(phydev, 0xa6e);

		ret = __phy_read(phydev, 0x16);

		rtl821x_write_page(phydev, 0);

	} else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) {

		rtl821x_write_page(phydev, 0xa6d);

		ret = __phy_read(phydev, 0x12);

		rtl821x_write_page(phydev, 0);

	} else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE2) {

		rtl821x_write_page(phydev, 0xa6d);

		ret = __phy_read(phydev, 0x10);

		rtl821x_write_page(phydev, 0);

	}



	return ret;

}



static int rtl8125_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,

			     u16 val)

{

	int ret = rtlgen_write_mmd(phydev, devnum, regnum, val);



	if (ret != -EOPNOTSUPP)

		return ret;



	if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) {

		rtl821x_write_page(phydev, 0xa6d);

		ret = __phy_write(phydev, 0x12, val);

		rtl821x_write_page(phydev, 0);

	}



	return ret;

}



static int rtl8125_get_features(struct phy_device *phydev)

{

	int val;
@@ -473,8 +514,8 @@ static struct phy_driver realtek_drvs[] = { 
		.resume		= genphy_resume,

		.read_page	= rtl821x_read_page,

		.write_page	= rtl821x_write_page,

		.read_mmd	= rtlgen_read_mmd,

		.write_mmd	= rtlgen_write_mmd,

		.read_mmd	= rtl8125_read_mmd,

		.write_mmd	= rtl8125_write_mmd,

	}, {

		PHY_ID_MATCH_EXACT(0x001cc961),

		.name		= "RTL8366RB Gigabit Ethernet",

include/uapi/linux/mdio.h

+10 −0
Original line number Diff line number Diff line
@@ -45,11 +45,14 @@ 
#define MDIO_AN_ADVERTISE	16	/* AN advertising (base page) */

#define MDIO_AN_LPA		19	/* AN LP abilities (base page) */

#define MDIO_PCS_EEE_ABLE	20	/* EEE Capability register */

#define MDIO_PCS_EEE_ABLE2	21	/* EEE Capability register 2 */

#define MDIO_PMA_NG_EXTABLE	21	/* 2.5G/5G PMA/PMD extended ability */

#define MDIO_PCS_EEE_WK_ERR	22	/* EEE wake error counter */

#define MDIO_PHYXS_LNSTAT	24	/* PHY XGXS lane state */

#define MDIO_AN_EEE_ADV		60	/* EEE advertisement */

#define MDIO_AN_EEE_LPABLE	61	/* EEE link partner ability */

#define MDIO_AN_EEE_ADV2	62	/* EEE advertisement 2 */

#define MDIO_AN_EEE_LPABLE2	63	/* EEE link partner ability 2 */



/* Media-dependent registers. */

#define MDIO_PMA_10GBT_SWAPPOL	130	/* 10GBASE-T pair swap & polarity */
@@ -276,6 +279,13 @@ 
#define MDIO_EEE_1000KX		0x0010	/* 1000KX EEE cap */

#define MDIO_EEE_10GKX4		0x0020	/* 10G KX4 EEE cap */

#define MDIO_EEE_10GKR		0x0040	/* 10G KR EEE cap */

#define MDIO_EEE_40GR_FW	0x0100	/* 40G R fast wake */

#define MDIO_EEE_40GR_DS	0x0200	/* 40G R deep sleep */

#define MDIO_EEE_100GR_FW	0x1000	/* 100G R fast wake */

#define MDIO_EEE_100GR_DS	0x2000	/* 100G R deep sleep */



#define MDIO_EEE_2_5GT		0x0001	/* 2.5GT EEE cap */

#define MDIO_EEE_5GT		0x0002	/* 5GT EEE cap */



/* 2.5G/5G Extended abilities register. */

#define MDIO_PMA_NG_EXTABLE_2_5GBT	0x0001	/* 2.5GBASET ability */

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