Commit 44b09b11 authored Sep 21, 2019 by Martin Blumenstingl Committed by Jerome Brunet Oct 01, 2019

clk: meson: gxbb: let sar_adc_clk_div set the parent clock rate

The meson-saradc driver manually sets the input clock for
sar_adc_clk_sel. Update the GXBB clock driver (which is used on GXBB,
GXL and GXM) so the rate settings on sar_adc_clk_div are propagated up
to sar_adc_clk_sel which will let the common clock framework select the
best matching parent clock if we want that.

This makes sar_adc_clk_div consistent with the axg-aoclk and g12a-aoclk
drivers, which both also specify CLK_SET_RATE_PARENT.

Fixes: 33d0fcdf ("clk: gxbb: add the SAR ADC clocks and expose them")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

parent 54ecb8f7

drivers/clk/meson/gxbb.c

+1 −0

Original line number	Diff line number	Diff line
		@@ -935,6 +935,7 @@ static struct clk_regmap gxbb_sar_adc_clk_div = {
		&gxbb_sar_adc_clk_sel.hw
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		},
		};

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