Commit 44b06a76 authored by Paul Cercueil's avatar Paul Cercueil Committed by Stephen Boyd
Browse files

clk: ingenic/jz4770: Fix incorrect dividers for main clocks 



The main clocks (cclk, h0clk, h1clk, h2clk, c1clk, pclk) were using
incorrect dividers, and thus reported an incorrect rate.

Signed-off-by: default avatarPaul Cercueil <paul@crapouillou.net>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 2a1a7036

drivers/clk/ingenic/jz4770-cgu.c

+28 −6
Original line number Diff line number Diff line
@@ -87,6 +87,10 @@ static const s8 pll_od_encoding[8] = { 
	0x0, 0x1, -1, 0x2, -1, -1, -1, 0x3,

};



static const u8 jz4770_cgu_cpccr_div_table[] = {

	1, 2, 3, 4, 6, 8, 12,

};



static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = {



	/* External clocks */
@@ -144,34 +148,52 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = { 
	[JZ4770_CLK_CCLK] = {

		"cclk", CGU_CLK_DIV,

		.parents = { JZ4770_CLK_PLL0, },

		.div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1 },

		.div = {

			CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1,

			jz4770_cgu_cpccr_div_table,

		},

	},

	[JZ4770_CLK_H0CLK] = {

		"h0clk", CGU_CLK_DIV,

		.parents = { JZ4770_CLK_PLL0, },

		.div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1 },

		.div = {

			CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1,

			jz4770_cgu_cpccr_div_table,

		},

	},

	[JZ4770_CLK_H1CLK] = {

		"h1clk", CGU_CLK_DIV | CGU_CLK_GATE,

		.parents = { JZ4770_CLK_PLL0, },

		.div = { CGU_REG_CPCCR, 24, 1, 4, 22, -1, -1 },

		.div = {

			CGU_REG_CPCCR, 24, 1, 4, 22, -1, -1,

			jz4770_cgu_cpccr_div_table,

		},

		.gate = { CGU_REG_CLKGR1, 7 },

	},

	[JZ4770_CLK_H2CLK] = {

		"h2clk", CGU_CLK_DIV,

		.parents = { JZ4770_CLK_PLL0, },

		.div = { CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1 },

		.div = {

			CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1,

			jz4770_cgu_cpccr_div_table,

		},

	},

	[JZ4770_CLK_C1CLK] = {

		"c1clk", CGU_CLK_DIV | CGU_CLK_GATE,

		.parents = { JZ4770_CLK_PLL0, },

		.div = { CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1 },

		.div = {

			CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1,

			jz4770_cgu_cpccr_div_table,

		},

		.gate = { CGU_REG_OPCR, 31, true }, // disable CCLK stop on idle

	},

	[JZ4770_CLK_PCLK] = {

		"pclk", CGU_CLK_DIV,

		.parents = { JZ4770_CLK_PLL0, },

		.div = { CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1 },

		.div = {

			CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1,

			jz4770_cgu_cpccr_div_table,

		},

	},



	/* Those divided clocks can connect to PLL0 or PLL1 */

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