Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net

		is invoked by both RCU-sched readers and updaters.

	srcu_dereference_check(p, c):

		Use explicit check expression "c" along with

		srcu_read_lock_held()().  This is useful in code that

		srcu_read_lock_held().  This is useful in code that

		is invoked by both SRCU readers and updaters.

	rcu_dereference_raw(p):

		Don't check.  (Use sparingly, if at all.)

  98 block	User-mode virtual block device

		  0 = /dev/ubda		First user-mode block device

		 16 = /dev/udbb		Second user-mode block device

		 16 = /dev/ubdb		Second user-mode block device

		    ...

		Partitions are handled in the same way as for IDE

DYTC Lapmode sensor

------------------

-------------------

sysfs: dytc_lapmode

internal P-state selection logic is expected to focus entirely on performance.

This will override the EPP/EPB setting coming from the ``sysfs`` interface

(see `Energy vs Performance Hints`_ below).

(see `Energy vs Performance Hints`_ below).  Moreover, any attempts to change

the EPP/EPB to a value different from 0 ("performance") via ``sysfs`` in this

configuration will be rejected.

Also, in this configuration the range of P-states available to the processor's

internal P-state selection logic is always restricted to the upper boundary

Energy-Performance Bias (EPB) knob. It is also possible to write a positive

integer value between 0 to 255, if the EPP feature is present. If the EPP

feature is not present, writing integer value to this attribute is not

supported. In this case, user can use

supported. In this case, user can use the

"/sys/devices/system/cpu/cpu*/power/energy_perf_bias" interface.

[Note that tasks may by migrated from one CPU to another by the scheduler's

Texas Instruments K3 Interrupt Aggregator

=========================================

The Interrupt Aggregator (INTA) provides a centralized machine

which handles the termination of system events to that they can

be coherently processed by the host(s) in the system. A maximum

of 64 events can be mapped to a single interrupt.

                              Interrupt Aggregator

                     +-----------------------------------------+

                     |      Intmap            VINT             |

                     | +--------------+  +------------+        |

            m ------>| | vint  | bit  |  | 0 |.....|63| vint0  |

               .     | +--------------+  +------------+        |       +------+

               .     |         .               .               |       | HOST |

Globalevents  ------>|         .               .               |------>| IRQ  |

               .     |         .               .               |       | CTRL |

               .     |         .               .               |       +------+

            n ------>| +--------------+  +------------+        |

                     | | vint  | bit  |  | 0 |.....|63| vintx  |

                     | +--------------+  +------------+        |

                     |                                         |

                     +-----------------------------------------+

Configuration of these Intmap registers that maps global events to vint is done

by a system controller (like the Device Memory and Security Controller on K3

AM654 SoC). Driver should request the system controller to get the range

of global events and vints assigned to the requesting host. Management

of these requested resources should be handled by driver and requests

system controller to map specific global event to vint, bit pair.

Communication between the host processor running an OS and the system

controller happens through a protocol called TI System Control Interface

(TISCI protocol). For more details refer:

Documentation/devicetree/bindings/arm/keystone/ti,sci.txt

TISCI Interrupt Aggregator Node:

-------------------------------

- compatible:		Must be "ti,sci-inta".

- reg:			Should contain registers location and length.

- interrupt-controller:	Identifies the node as an interrupt controller

- msi-controller:	Identifies the node as an MSI controller.

- interrupt-parent:	phandle of irq parent.

- ti,sci:		Phandle to TI-SCI compatible System controller node.

- ti,sci-dev-id:	TISCI device ID of the Interrupt Aggregator.

- ti,sci-rm-range-vint:	Array of TISCI subtype ids representing vints(inta

			outputs) range within this INTA, assigned to the

			requesting host context.

- ti,sci-rm-range-global-event:	Array of TISCI subtype ids representing the

			global events range reaching this IA and are assigned

			to the requesting host context.

Example:

--------

main_udmass_inta: interrupt-controller@33d00000 {

	compatible = "ti,sci-inta";

	reg = <0x0 0x33d00000 0x0 0x100000>;

	interrupt-controller;

	msi-controller;

	interrupt-parent = <&main_navss_intr>;

	ti,sci = <&dmsc>;

	ti,sci-dev-id = <179>;

	ti,sci-rm-range-vint = <0x0>;

	ti,sci-rm-range-global-event = <0x1>;

};