Commit 44982735 authored by Peter Ujfalusi's avatar Peter Ujfalusi Committed by Mark Brown
Browse files

ASoC: davinci-mcasp: Correct RX start sequence 



Follow the sequence described in the TRMs when starting RX.
Write to RXBUF register was not correct and there is no need to release the
RX state machine/Receive frame sync generator twice.

Signed-off-by: default avatarPeter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 36bcecd0

sound/soc/davinci/davinci-mcasp.c

+4 −8
Original line number Diff line number Diff line
@@ -154,9 +154,9 @@ static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp) 


static void mcasp_start_rx(struct davinci_mcasp *mcasp)

{

	/* Start clocks */

	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);

	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);



	/*

	 * When ASYNC == 0 the transmit and receive sections operate

	 * synchronously from the transmit clock and frame sync. We need to make
@@ -167,16 +167,12 @@ static void mcasp_start_rx(struct davinci_mcasp *mcasp) 
		mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);

	}



	/* Activate serializer(s) */

	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);

	mcasp_set_reg(mcasp, DAVINCI_MCASP_RXBUF_REG, 0);



	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);

	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);

	mcasp_set_reg(mcasp, DAVINCI_MCASP_RXBUF_REG, 0);



	/* Release RX state machine */

	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);

	/* Release Frame Sync generator */

	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);



	if (mcasp_is_synchronous(mcasp))

		mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);

}

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