Commit 448d64f8 authored by Paul Mackerras's avatar Paul Mackerras Committed by Ingo Molnar
Browse files

perf_counter: powerpc: Use unsigned long for register and constraint values 



This changes the powerpc perf_counter back-end to use unsigned long
types for hardware register values and for the value/mask pairs used
in checking whether a given set of events fit within the hardware
constraints.  This is in preparation for adding support for the PMU
on some 32-bit powerpc processors.  On 32-bit processors the hardware
registers are only 32 bits wide, and the PMU structure is generally
simpler, so 32 bits should be ample for expressing the hardware
constraints.  On 64-bit processors, unsigned long is 64 bits wide,
so using unsigned long vs. u64 (unsigned long long) makes no actual
difference.

This makes some other very minor changes: adjusting whitespace to line
things up in initialized structures, and simplifying some code in
hw_perf_disable().

Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: linuxppc-dev@ozlabs.org
Cc: benh@kernel.crashing.org
LKML-Reference: <19000.55473.26174.331511@cargo.ozlabs.ibm.com>
Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
parent 105988c0

arch/powerpc/include/asm/perf_counter.h

+18 −17
Original line number Diff line number Diff line
@@ -23,14 +23,15 @@ 
struct power_pmu {

	int		n_counter;

	int		max_alternatives;

	u64	add_fields;

	u64	test_adder;

	unsigned long	add_fields;

	unsigned long	test_adder;

	int		(*compute_mmcr)(u64 events[], int n_ev,

				unsigned int hwc[], u64 mmcr[]);

	int	(*get_constraint)(u64 event, u64 *mskp, u64 *valp);

				unsigned int hwc[], unsigned long mmcr[]);

	int		(*get_constraint)(u64 event, unsigned long *mskp,

				unsigned long *valp);

	int		(*get_alternatives)(u64 event, unsigned int flags,

				u64 alt[]);

	void	(*disable_pmc)(unsigned int pmc, u64 mmcr[]);

	void		(*disable_pmc)(unsigned int pmc, unsigned long mmcr[]);

	int		(*limited_pmc_event)(u64 event);

	u32		flags;

	int		n_generic;
@@ -68,8 +69,8 @@ extern unsigned long perf_instruction_pointer(struct pt_regs *regs); 
#endif



/*

 * The power_pmu.get_constraint function returns a 64-bit value and

 * a 64-bit mask that express the constraints between this event and

 * The power_pmu.get_constraint function returns a 32/64-bit value and

 * a 32/64-bit mask that express the constraints between this event and

 * other events.

 *

 * The value and mask are divided up into (non-overlapping) bitfields

arch/powerpc/kernel/perf_counter.c

+9 −11
Original line number Diff line number Diff line
@@ -29,7 +29,7 @@ struct cpu_hw_counters { 
	struct perf_counter *counter[MAX_HWCOUNTERS];

	u64 events[MAX_HWCOUNTERS];

	unsigned int flags[MAX_HWCOUNTERS];

	u64 mmcr[3];

	unsigned long mmcr[3];

	struct perf_counter *limited_counter[MAX_LIMITED_HWCOUNTERS];

	u8  limited_hwidx[MAX_LIMITED_HWCOUNTERS];

};
@@ -135,15 +135,15 @@ static void write_pmc(int idx, unsigned long val) 
static int power_check_constraints(u64 event[], unsigned int cflags[],

				   int n_ev)

{

	u64 mask, value, nv;

	unsigned long mask, value, nv;

	u64 alternatives[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES];

	u64 amasks[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES];

	u64 avalues[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES];

	u64 smasks[MAX_HWCOUNTERS], svalues[MAX_HWCOUNTERS];

	unsigned long amasks[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES];

	unsigned long avalues[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES];

	unsigned long smasks[MAX_HWCOUNTERS], svalues[MAX_HWCOUNTERS];

	int n_alt[MAX_HWCOUNTERS], choice[MAX_HWCOUNTERS];

	int i, j;

	u64 addf = ppmu->add_fields;

	u64 tadd = ppmu->test_adder;

	unsigned long addf = ppmu->add_fields;

	unsigned long tadd = ppmu->test_adder;



	if (n_ev > ppmu->n_counter)

		return -1;
@@ -403,14 +403,12 @@ static void write_mmcr0(struct cpu_hw_counters *cpuhw, unsigned long mmcr0) 
void hw_perf_disable(void)

{

	struct cpu_hw_counters *cpuhw;

	unsigned long ret;

	unsigned long flags;



	local_irq_save(flags);

	cpuhw = &__get_cpu_var(cpu_hw_counters);



	ret = cpuhw->disabled;

	if (!ret) {

	if (!cpuhw->disabled) {

		cpuhw->disabled = 1;

		cpuhw->n_added = 0;
@@ -1013,9 +1011,9 @@ static void record_and_restart(struct perf_counter *counter, long val, 
			       struct pt_regs *regs, int nmi)

{

	u64 period = counter->hw.sample_period;

	unsigned long mmcra, sdsync;

	s64 prev, delta, left;

	int record = 0;

	u64 mmcra, sdsync;



	/* we don't have to worry about interrupts here */

	prev = atomic64_read(&counter->hw.prev_count);

arch/powerpc/kernel/power4-pmu.c

+39 −35
Original line number Diff line number Diff line
@@ -179,22 +179,22 @@ static short mmcr1_adder_bits[8] = { 
 */



static struct unitinfo {

	u64	value, mask;

	unsigned long	value, mask;

	int		unit;

	int		lowerbit;

} p4_unitinfo[16] = {

	[PM_FPU]  = { 0x44000000000000ull, 0x88000000000000ull, PM_FPU, 0 },

	[PM_ISU1] = { 0x20080000000000ull, 0x88000000000000ull, PM_ISU1, 0 },

	[PM_FPU]  = { 0x44000000000000ul, 0x88000000000000ul, PM_FPU, 0 },

	[PM_ISU1] = { 0x20080000000000ul, 0x88000000000000ul, PM_ISU1, 0 },

	[PM_ISU1_ALT] =

		    { 0x20080000000000ull, 0x88000000000000ull, PM_ISU1, 0 },

	[PM_IFU]  = { 0x02200000000000ull, 0x08820000000000ull, PM_IFU, 41 },

		    { 0x20080000000000ul, 0x88000000000000ul, PM_ISU1, 0 },

	[PM_IFU]  = { 0x02200000000000ul, 0x08820000000000ul, PM_IFU, 41 },

	[PM_IFU_ALT] =

		    { 0x02200000000000ull, 0x08820000000000ull, PM_IFU, 41 },

	[PM_IDU0] = { 0x10100000000000ull, 0x80840000000000ull, PM_IDU0, 1 },

	[PM_ISU2] = { 0x10140000000000ull, 0x80840000000000ull, PM_ISU2, 0 },

	[PM_LSU0] = { 0x01400000000000ull, 0x08800000000000ull, PM_LSU0, 0 },

	[PM_LSU1] = { 0x00000000000000ull, 0x00010000000000ull, PM_LSU1, 40 },

	[PM_GPS]  = { 0x00000000000000ull, 0x00000000000000ull, PM_GPS, 0 }

		    { 0x02200000000000ul, 0x08820000000000ul, PM_IFU, 41 },

	[PM_IDU0] = { 0x10100000000000ul, 0x80840000000000ul, PM_IDU0, 1 },

	[PM_ISU2] = { 0x10140000000000ul, 0x80840000000000ul, PM_ISU2, 0 },

	[PM_LSU0] = { 0x01400000000000ul, 0x08800000000000ul, PM_LSU0, 0 },

	[PM_LSU1] = { 0x00000000000000ul, 0x00010000000000ul, PM_LSU1, 40 },

	[PM_GPS]  = { 0x00000000000000ul, 0x00000000000000ul, PM_GPS, 0 }

};



static unsigned char direct_marked_event[8] = {
@@ -249,10 +249,11 @@ static int p4_marked_instr_event(u64 event) 
	return (mask >> (byte * 8 + bit)) & 1;

}



static int p4_get_constraint(u64 event, u64 *maskp, u64 *valp)

static int p4_get_constraint(u64 event, unsigned long *maskp,

			     unsigned long *valp)

{

	int pmc, byte, unit, lower, sh;

	u64 mask = 0, value = 0;

	unsigned long mask = 0, value = 0;

	int grp = -1;



	pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
@@ -282,14 +283,14 @@ static int p4_get_constraint(u64 event, u64 *maskp, u64 *valp) 
		value |= p4_unitinfo[unit].value;

		sh = p4_unitinfo[unit].lowerbit;

		if (sh > 1)

			value |= (u64)lower << sh;

			value |= (unsigned long)lower << sh;

		else if (lower != sh)

			return -1;

		unit = p4_unitinfo[unit].unit;



		/* Set byte lane select field */

		mask  |= 0xfULL << (28 - 4 * byte);

		value |= (u64)unit << (28 - 4 * byte);

		value |= (unsigned long)unit << (28 - 4 * byte);

	}

	if (grp == 0) {

		/* increment PMC1/2/5/6 field */
@@ -353,9 +354,9 @@ static int p4_get_alternatives(u64 event, unsigned int flags, u64 alt[]) 
}



static int p4_compute_mmcr(u64 event[], int n_ev,

			   unsigned int hwc[], u64 mmcr[])

			   unsigned int hwc[], unsigned long mmcr[])

{

	u64 mmcr0 = 0, mmcr1 = 0, mmcra = 0;

	unsigned long mmcr0 = 0, mmcr1 = 0, mmcra = 0;

	unsigned int pmc, unit, byte, psel, lower;

	unsigned int ttm, grp;

	unsigned int pmc_inuse = 0;
@@ -429,9 +430,11 @@ static int p4_compute_mmcr(u64 event[], int n_ev, 
		return -1;



	/* Set TTMxSEL fields.  Note, units 1-3 => TTM0SEL codes 0-2 */

	mmcr1 |= (u64)(unituse[3] * 2 + unituse[2]) << MMCR1_TTM0SEL_SH;

	mmcr1 |= (u64)(unituse[7] * 3 + unituse[6] * 2) << MMCR1_TTM1SEL_SH;

	mmcr1 |= (u64)unituse[9] << MMCR1_TTM2SEL_SH;

	mmcr1 |= (unsigned long)(unituse[3] * 2 + unituse[2])

		<< MMCR1_TTM0SEL_SH;

	mmcr1 |= (unsigned long)(unituse[7] * 3 + unituse[6] * 2)

		<< MMCR1_TTM1SEL_SH;

	mmcr1 |= (unsigned long)unituse[9] << MMCR1_TTM2SEL_SH;



	/* Set TTCxSEL fields. */

	if (unitlower & 0xe)
@@ -456,7 +459,8 @@ static int p4_compute_mmcr(u64 event[], int n_ev, 
				ttm = unit - 1;		/* 2->1, 3->2 */

			else

				ttm = unit >> 2;

			mmcr1 |= (u64)ttm << (MMCR1_TD_CP_DBG0SEL_SH - 2*byte);

			mmcr1 |= (unsigned long)ttm

				<< (MMCR1_TD_CP_DBG0SEL_SH - 2 * byte);

		}

	}
@@ -519,7 +523,7 @@ static int p4_compute_mmcr(u64 event[], int n_ev, 
	return 0;

}



static void p4_disable_pmc(unsigned int pmc, u64 mmcr[])

static void p4_disable_pmc(unsigned int pmc, unsigned long mmcr[])

{

	/*

	 * Setting the PMCxSEL field to 0 disables PMC x.
@@ -586,8 +590,8 @@ static int power4_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { 
struct power_pmu power4_pmu = {

	.n_counter		= 8,

	.max_alternatives	= 5,

	.add_fields = 0x0000001100005555ull,

	.test_adder = 0x0011083300000000ull,

	.add_fields		= 0x0000001100005555ul,

	.test_adder		= 0x0011083300000000ul,

	.compute_mmcr		= p4_compute_mmcr,

	.get_constraint		= p4_get_constraint,

	.get_alternatives	= p4_get_alternatives,

arch/powerpc/kernel/power5+-pmu.c

+41 −38
Original line number Diff line number Diff line
@@ -126,20 +126,21 @@ static const int grsel_shift[8] = { 
};



/* Masks and values for using events from the various units */

static u64 unit_cons[PM_LASTUNIT+1][2] = {

	[PM_FPU] =   { 0x3200000000ull, 0x0100000000ull },

	[PM_ISU0] =  { 0x0200000000ull, 0x0080000000ull },

	[PM_ISU1] =  { 0x3200000000ull, 0x3100000000ull },

	[PM_IFU] =   { 0x3200000000ull, 0x2100000000ull },

	[PM_IDU] =   { 0x0e00000000ull, 0x0040000000ull },

	[PM_GRS] =   { 0x0e00000000ull, 0x0c40000000ull },

static unsigned long unit_cons[PM_LASTUNIT+1][2] = {

	[PM_FPU] =   { 0x3200000000ul, 0x0100000000ul },

	[PM_ISU0] =  { 0x0200000000ul, 0x0080000000ul },

	[PM_ISU1] =  { 0x3200000000ul, 0x3100000000ul },

	[PM_IFU] =   { 0x3200000000ul, 0x2100000000ul },

	[PM_IDU] =   { 0x0e00000000ul, 0x0040000000ul },

	[PM_GRS] =   { 0x0e00000000ul, 0x0c40000000ul },

};



static int power5p_get_constraint(u64 event, u64 *maskp, u64 *valp)

static int power5p_get_constraint(u64 event, unsigned long *maskp,

				  unsigned long *valp)

{

	int pmc, byte, unit, sh;

	int bit, fmask;

	u64 mask = 0, value = 0;

	unsigned long mask = 0, value = 0;



	pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;

	if (pmc) {
@@ -171,17 +172,18 @@ static int power5p_get_constraint(u64 event, u64 *maskp, u64 *valp) 
			bit = event & 7;

			fmask = (bit == 6)? 7: 3;

			sh = grsel_shift[bit];

			mask |= (u64)fmask << sh;

			value |= (u64)((event >> PM_GRS_SH) & fmask) << sh;

			mask |= (unsigned long)fmask << sh;

			value |= (unsigned long)((event >> PM_GRS_SH) & fmask)

				<< sh;

		}

		/* Set byte lane select field */

		mask  |= 0xfULL << (24 - 4 * byte);

		value |= (u64)unit << (24 - 4 * byte);

		mask  |= 0xfUL << (24 - 4 * byte);

		value |= (unsigned long)unit << (24 - 4 * byte);

	}

	if (pmc < 5) {

		/* need a counter from PMC1-4 set */

		mask  |= 0x8000000000000ull;

		value |= 0x1000000000000ull;

		mask  |= 0x8000000000000ul;

		value |= 0x1000000000000ul;

	}

	*maskp = mask;

	*valp = value;
@@ -452,10 +454,10 @@ static int power5p_marked_instr_event(u64 event) 
}



static int power5p_compute_mmcr(u64 event[], int n_ev,

				unsigned int hwc[], u64 mmcr[])

				unsigned int hwc[], unsigned long mmcr[])

{

	u64 mmcr1 = 0;

	u64 mmcra = 0;

	unsigned long mmcr1 = 0;

	unsigned long mmcra = 0;

	unsigned int pmc, unit, byte, psel;

	unsigned int ttm;

	int i, isbus, bit, grsel;
@@ -517,7 +519,7 @@ static int power5p_compute_mmcr(u64 event[], int n_ev, 
			continue;

		if (ttmuse++)

			return -1;

		mmcr1 |= (u64)i << MMCR1_TTM0SEL_SH;

		mmcr1 |= (unsigned long)i << MMCR1_TTM0SEL_SH;

	}

	ttmuse = 0;

	for (; i <= PM_GRS; ++i) {
@@ -525,7 +527,7 @@ static int power5p_compute_mmcr(u64 event[], int n_ev, 
			continue;

		if (ttmuse++)

			return -1;

		mmcr1 |= (u64)(i & 3) << MMCR1_TTM1SEL_SH;

		mmcr1 |= (unsigned long)(i & 3) << MMCR1_TTM1SEL_SH;

	}

	if (ttmuse > 1)

		return -1;
@@ -540,10 +542,11 @@ static int power5p_compute_mmcr(u64 event[], int n_ev, 
			unit = PM_ISU0_ALT;

		} else if (unit == PM_LSU1 + 1) {

			/* select lower word of LSU1 for this byte */

			mmcr1 |= 1ull << (MMCR1_TTM3SEL_SH + 3 - byte);

			mmcr1 |= 1ul << (MMCR1_TTM3SEL_SH + 3 - byte);

		}

		ttm = unit >> 2;

		mmcr1 |= (u64)ttm << (MMCR1_TD_CP_DBG0SEL_SH - 2 * byte);

		mmcr1 |= (unsigned long)ttm

			<< (MMCR1_TD_CP_DBG0SEL_SH - 2 * byte);

	}



	/* Second pass: assign PMCs, set PMCxSEL and PMCx_ADDER_SEL fields */
@@ -568,7 +571,7 @@ static int power5p_compute_mmcr(u64 event[], int n_ev, 
			if (isbus && (byte & 2) &&

			    (psel == 8 || psel == 0x10 || psel == 0x28))

				/* add events on higher-numbered bus */

				mmcr1 |= 1ull << (MMCR1_PMC1_ADDER_SEL_SH - pmc);

				mmcr1 |= 1ul << (MMCR1_PMC1_ADDER_SEL_SH - pmc);

		} else {

			/* Instructions or run cycles on PMC5/6 */

			--pmc;
@@ -576,7 +579,7 @@ static int power5p_compute_mmcr(u64 event[], int n_ev, 
		if (isbus && unit == PM_GRS) {

			bit = psel & 7;

			grsel = (event[i] >> PM_GRS_SH) & PM_GRS_MSK;

			mmcr1 |= (u64)grsel << grsel_shift[bit];

			mmcr1 |= (unsigned long)grsel << grsel_shift[bit];

		}

		if (power5p_marked_instr_event(event[i]))

			mmcra |= MMCRA_SAMPLE_ENABLE;
@@ -599,7 +602,7 @@ static int power5p_compute_mmcr(u64 event[], int n_ev, 
	return 0;

}



static void power5p_disable_pmc(unsigned int pmc, u64 mmcr[])

static void power5p_disable_pmc(unsigned int pmc, unsigned long mmcr[])

{

	if (pmc <= 3)

		mmcr[1] &= ~(0x7fUL << MMCR1_PMCSEL_SH(pmc));
@@ -657,8 +660,8 @@ static int power5p_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { 
struct power_pmu power5p_pmu = {

	.n_counter		= 6,

	.max_alternatives	= MAX_ALT,

	.add_fields = 0x7000000000055ull,

	.test_adder = 0x3000040000000ull,

	.add_fields		= 0x7000000000055ul,

	.test_adder		= 0x3000040000000ul,

	.compute_mmcr		= power5p_compute_mmcr,

	.get_constraint		= power5p_get_constraint,

	.get_alternatives	= power5p_get_alternatives,

arch/powerpc/kernel/power5-pmu.c

+43 −40
Original line number Diff line number Diff line
@@ -130,20 +130,21 @@ static const int grsel_shift[8] = { 
};



/* Masks and values for using events from the various units */

static u64 unit_cons[PM_LASTUNIT+1][2] = {

	[PM_FPU] =   { 0xc0002000000000ull, 0x00001000000000ull },

	[PM_ISU0] =  { 0x00002000000000ull, 0x00000800000000ull },

	[PM_ISU1] =  { 0xc0002000000000ull, 0xc0001000000000ull },

	[PM_IFU] =   { 0xc0002000000000ull, 0x80001000000000ull },

	[PM_IDU] =   { 0x30002000000000ull, 0x00000400000000ull },

	[PM_GRS] =   { 0x30002000000000ull, 0x30000400000000ull },

static unsigned long unit_cons[PM_LASTUNIT+1][2] = {

	[PM_FPU] =   { 0xc0002000000000ul, 0x00001000000000ul },

	[PM_ISU0] =  { 0x00002000000000ul, 0x00000800000000ul },

	[PM_ISU1] =  { 0xc0002000000000ul, 0xc0001000000000ul },

	[PM_IFU] =   { 0xc0002000000000ul, 0x80001000000000ul },

	[PM_IDU] =   { 0x30002000000000ul, 0x00000400000000ul },

	[PM_GRS] =   { 0x30002000000000ul, 0x30000400000000ul },

};



static int power5_get_constraint(u64 event, u64 *maskp, u64 *valp)

static int power5_get_constraint(u64 event, unsigned long *maskp,

				 unsigned long *valp)

{

	int pmc, byte, unit, sh;

	int bit, fmask;

	u64 mask = 0, value = 0;

	unsigned long mask = 0, value = 0;

	int grp = -1;



	pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
@@ -178,8 +179,9 @@ static int power5_get_constraint(u64 event, u64 *maskp, u64 *valp) 
			bit = event & 7;

			fmask = (bit == 6)? 7: 3;

			sh = grsel_shift[bit];

			mask |= (u64)fmask << sh;

			value |= (u64)((event >> PM_GRS_SH) & fmask) << sh;

			mask |= (unsigned long)fmask << sh;

			value |= (unsigned long)((event >> PM_GRS_SH) & fmask)

				<< sh;

		}

		/*

		 * Bus events on bytes 0 and 2 can be counted
@@ -188,22 +190,22 @@ static int power5_get_constraint(u64 event, u64 *maskp, u64 *valp) 
		if (!pmc)

			grp = byte & 1;

		/* Set byte lane select field */

		mask  |= 0xfULL << (24 - 4 * byte);

		value |= (u64)unit << (24 - 4 * byte);

		mask  |= 0xfUL << (24 - 4 * byte);

		value |= (unsigned long)unit << (24 - 4 * byte);

	}

	if (grp == 0) {

		/* increment PMC1/2 field */

		mask  |= 0x200000000ull;

		value |= 0x080000000ull;

		mask  |= 0x200000000ul;

		value |= 0x080000000ul;

	} else if (grp == 1) {

		/* increment PMC3/4 field */

		mask  |= 0x40000000ull;

		value |= 0x10000000ull;

		mask  |= 0x40000000ul;

		value |= 0x10000000ul;

	}

	if (pmc < 5) {

		/* need a counter from PMC1-4 set */

		mask  |= 0x8000000000000ull;

		value |= 0x1000000000000ull;

		mask  |= 0x8000000000000ul;

		value |= 0x1000000000000ul;

	}

	*maskp = mask;

	*valp = value;
@@ -383,10 +385,10 @@ static int power5_marked_instr_event(u64 event) 
}



static int power5_compute_mmcr(u64 event[], int n_ev,

			       unsigned int hwc[], u64 mmcr[])

			       unsigned int hwc[], unsigned long mmcr[])

{

	u64 mmcr1 = 0;

	u64 mmcra = 0;

	unsigned long mmcr1 = 0;

	unsigned long mmcra = 0;

	unsigned int pmc, unit, byte, psel;

	unsigned int ttm, grp;

	int i, isbus, bit, grsel;
@@ -457,7 +459,7 @@ static int power5_compute_mmcr(u64 event[], int n_ev, 
			continue;

		if (ttmuse++)

			return -1;

		mmcr1 |= (u64)i << MMCR1_TTM0SEL_SH;

		mmcr1 |= (unsigned long)i << MMCR1_TTM0SEL_SH;

	}

	ttmuse = 0;

	for (; i <= PM_GRS; ++i) {
@@ -465,7 +467,7 @@ static int power5_compute_mmcr(u64 event[], int n_ev, 
			continue;

		if (ttmuse++)

			return -1;

		mmcr1 |= (u64)(i & 3) << MMCR1_TTM1SEL_SH;

		mmcr1 |= (unsigned long)(i & 3) << MMCR1_TTM1SEL_SH;

	}

	if (ttmuse > 1)

		return -1;
@@ -480,10 +482,11 @@ static int power5_compute_mmcr(u64 event[], int n_ev, 
			unit = PM_ISU0_ALT;

		} else if (unit == PM_LSU1 + 1) {

			/* select lower word of LSU1 for this byte */

			mmcr1 |= 1ull << (MMCR1_TTM3SEL_SH + 3 - byte);

			mmcr1 |= 1ul << (MMCR1_TTM3SEL_SH + 3 - byte);

		}

		ttm = unit >> 2;

		mmcr1 |= (u64)ttm << (MMCR1_TD_CP_DBG0SEL_SH - 2 * byte);

		mmcr1 |= (unsigned long)ttm

			<< (MMCR1_TD_CP_DBG0SEL_SH - 2 * byte);

	}



	/* Second pass: assign PMCs, set PMCxSEL and PMCx_ADDER_SEL fields */
@@ -513,7 +516,7 @@ static int power5_compute_mmcr(u64 event[], int n_ev, 
			--pmc;

			if ((psel == 8 || psel == 0x10) && isbus && (byte & 2))

				/* add events on higher-numbered bus */

				mmcr1 |= 1ull << (MMCR1_PMC1_ADDER_SEL_SH - pmc);

				mmcr1 |= 1ul << (MMCR1_PMC1_ADDER_SEL_SH - pmc);

		} else {

			/* Instructions or run cycles on PMC5/6 */

			--pmc;
@@ -521,7 +524,7 @@ static int power5_compute_mmcr(u64 event[], int n_ev, 
		if (isbus && unit == PM_GRS) {

			bit = psel & 7;

			grsel = (event[i] >> PM_GRS_SH) & PM_GRS_MSK;

			mmcr1 |= (u64)grsel << grsel_shift[bit];

			mmcr1 |= (unsigned long)grsel << grsel_shift[bit];

		}

		if (power5_marked_instr_event(event[i]))

			mmcra |= MMCRA_SAMPLE_ENABLE;
@@ -541,7 +544,7 @@ static int power5_compute_mmcr(u64 event[], int n_ev, 
	return 0;

}



static void power5_disable_pmc(unsigned int pmc, u64 mmcr[])

static void power5_disable_pmc(unsigned int pmc, unsigned long mmcr[])

{

	if (pmc <= 3)

		mmcr[1] &= ~(0x7fUL << MMCR1_PMCSEL_SH(pmc));
@@ -599,8 +602,8 @@ static int power5_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { 
struct power_pmu power5_pmu = {

	.n_counter		= 6,

	.max_alternatives	= MAX_ALT,

	.add_fields = 0x7000090000555ull,

	.test_adder = 0x3000490000000ull,

	.add_fields		= 0x7000090000555ul,

	.test_adder		= 0x3000490000000ul,

	.compute_mmcr		= power5_compute_mmcr,

	.get_constraint		= power5_get_constraint,

	.get_alternatives	= power5_get_alternatives,

CRA Git | Maintained and supported by SUSTech CRA and CCSE