Commit 4454c069 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge branch 'for_5.5/keystone-dts' of...

Merge branch 'for_5.5/keystone-dts' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone into arm/dt

* 'for_5.5/keystone-dts' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone:
  ARM: configs: keystone: enable cpts
  ARM: dts: k2l-netcp: add cpts refclk_mux node
  ARM: dts: k2hk-netcp: add cpts refclk_mux node
  ARM: dts: k2e-netcp: add cpts refclk_mux node
  ARM: dts: k2e-clocks: add input ext. fixed clocks tsipclka/b
  ARM: dts: keystone-clocks: add input fixed clocks

Link: https://lore.kernel.org/r/1572372856-20598-2-git-send-email-santosh.shilimkar@oracle.com


Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 3760828a cfc0e76b
Loading
Loading
Loading
Loading
+27 −0
Original line number Diff line number Diff line
@@ -408,4 +408,31 @@ clocks {
		reg-names = "control", "domain";
		domain-id = <0>;
	};

	/*
	 * Below are set of fixed, input clocks definitions,
	 * for which real frequencies have to be defined in board files.
	 * Those clocks can be used as reference clocks for some HW modules
	 * (as cpts, for example) by configuring corresponding clock muxes.
	 */
	timi0: timi0 {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <0>;
		clock-output-names = "timi0";
	};

	timi1: timi1 {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <0>;
		clock-output-names = "timi1";
	};

	tsrefclk: tsrefclk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <0>;
		clock-output-names = "tsrefclk";
	};
};
+20 −0
Original line number Diff line number Diff line
@@ -71,4 +71,24 @@ clocks {
		reg-names = "control", "domain";
		domain-id = <29>;
	};

	/*
	 * Below are set of fixed, input clocks definitions,
	 * for which real frequencies have to be defined in board files.
	 * Those clocks can be used as reference clocks for some HW modules
	 * (as cpts, for example) by configuring corresponding clock muxes.
	 */
	tsipclka: tsipclka {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <0>;
		clock-output-names = "tsipclka";
	};

	tsipclkb: tsipclkb {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <0>;
		clock-output-names = "tsipclkb";
	};
};
+19 −2
Original line number Diff line number Diff line
@@ -135,8 +135,8 @@ netcp: netcp@24000000 {
	/* NetCP address range */
	ranges = <0 0x24000000 0x1000000>;

	clocks = <&clkpa>, <&clkcpgmac>, <&chipclk12>;
	clock-names = "pa_clk", "ethss_clk", "cpts";
	clocks = <&clkpa>, <&clkcpgmac>;
	clock-names = "pa_clk", "ethss_clk";
	dma-coherent;

	ti,navigator-dmas = <&dma_gbe 0>,
@@ -156,6 +156,23 @@ netcp: netcp@24000000 {
			tx-queue = <896>;
			tx-channel = "nettx";

			cpts {
				clocks = <&cpts_refclk_mux>;
				clock-names = "cpts";

				cpts_refclk_mux: cpts-refclk-mux {
					#clock-cells = <0>;
					clocks = <&chipclk12>, <&chipclk13>,
						 <&timi0>, <&timi1>,
						 <&tsipclka>, <&tsrefclk>,
						 <&tsipclkb>;
					ti,mux-tbl = <0x0>, <0x1>, <0x2>,
						<0x3>, <0x4>, <0x8>, <0xC>;
					assigned-clocks = <&cpts_refclk_mux>;
					assigned-clock-parents = <&chipclk12>;
				};
			};

			interfaces {
				gbe0: interface-0 {
					slave-port = <0>;
+18 −2
Original line number Diff line number Diff line
@@ -152,8 +152,8 @@ netcp: netcp@2000000 {
	/* NetCP address range */
	ranges  = <0 0x2000000 0x100000>;

	clocks = <&clkpa>, <&clkcpgmac>, <&chipclk12>;
	clock-names = "pa_clk", "ethss_clk", "cpts";
	clocks = <&clkpa>, <&clkcpgmac>;
	clock-names = "pa_clk", "ethss_clk";
	dma-coherent;

	ti,navigator-dmas = <&dma_gbe 22>,
@@ -175,6 +175,22 @@ netcp: netcp@2000000 {
			tx-queue = <648>;
			tx-channel = "nettx";

			cpts {
				clocks = <&cpts_refclk_mux>;
				clock-names = "cpts";

				cpts_refclk_mux: cpts-refclk-mux {
					#clock-cells = <0>;
					clocks = <&chipclk12>, <&chipclk13>,
						 <&timi0>, <&timi1>,
						 <&tsrefclk>;
					ti,mux-tbl = <0x0>, <0x1>, <0x2>,
						<0x3>, <0x8>;
					assigned-clocks = <&cpts_refclk_mux>;
					assigned-clock-parents = <&chipclk12>;
				};
			};

			interfaces {
				gbe0: interface-0 {
					slave-port = <0>;
+18 −2
Original line number Diff line number Diff line
@@ -134,8 +134,8 @@ netcp: netcp@26000000 {
	/* NetCP address range */
	ranges = <0 0x26000000 0x1000000>;

	clocks = <&clkpa>, <&clkcpgmac>, <&chipclk12>;
	clock-names = "pa_clk", "ethss_clk", "cpts";
	clocks = <&clkpa>, <&clkcpgmac>;
	clock-names = "pa_clk", "ethss_clk";
	dma-coherent;

	ti,navigator-dmas = <&dma_gbe 0>,
@@ -155,6 +155,22 @@ netcp: netcp@26000000 {
			tx-queue = <896>;
			tx-channel = "nettx";

			cpts {
				clocks = <&cpts_refclk_mux>;
				clock-names = "cpts";

				cpts_refclk_mux: cpts-refclk-mux {
					#clock-cells = <0>;
					clocks = <&chipclk12>, <&chipclk13>,
						 <&timi0>, <&timi1>,
						 <&tsrefclk>;
					ti,mux-tbl = <0x0>, <0x1>, <0x2>,
						<0x3>, <0x8>;
					assigned-clocks = <&cpts_refclk_mux>;
					assigned-clock-parents = <&chipclk12>;
				};
			};

			interfaces {
				gbe0: interface-0 {
					slave-port = <0>;
Loading