Commit 444f9a80 authored by Joseph Lo's avatar Joseph Lo Committed by Stephen Warren
Browse files

ARM: tegra: config the polarity of the request of sys clock 



When suspending to LP1 mode, the SYSCLK will be clock gated. And different
board may have different polarity of the request of SYSCLK, this patch
configure the polarity from the DT for the board.

Signed-off-by: default avatarJoseph Lo <josephl@nvidia.com>
Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
parent 5b795d05

arch/arm/mach-tegra/pmc.c

+16 −0
Original line number Diff line number Diff line
@@ -27,6 +27,8 @@ 
#include "pmc.h"

#include "sleep.h"



#define TEGRA_POWER_SYSCLK_POLARITY	(1 << 10)  /* sys clk polarity */

#define TEGRA_POWER_SYSCLK_OE		(1 << 11)  /* system clock enable */

#define TEGRA_POWER_EFFECT_LP0		(1 << 14)  /* LP0 when CPU pwr gated */

#define TEGRA_POWER_CPU_PWRREQ_POLARITY	(1 << 15)  /* CPU pwr req polarity */

#define TEGRA_POWER_CPU_PWRREQ_OE	(1 << 16)  /* CPU pwr req enable */
@@ -238,6 +240,20 @@ void tegra_pmc_suspend_init(void) 
	reg = tegra_pmc_readl(PMC_CTRL);

	reg |= TEGRA_POWER_CPU_PWRREQ_OE;

	tegra_pmc_writel(reg, PMC_CTRL);



	reg = tegra_pmc_readl(PMC_CTRL);



	if (!pmc_pm_data.sysclkreq_high)

		reg |= TEGRA_POWER_SYSCLK_POLARITY;

	else

		reg &= ~TEGRA_POWER_SYSCLK_POLARITY;



	/* configure the output polarity while the request is tristated */

	tegra_pmc_writel(reg, PMC_CTRL);



	/* now enable the request */

	reg |= TEGRA_POWER_SYSCLK_OE;

	tegra_pmc_writel(reg, PMC_CTRL);

}

#endif

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