Commit 44448640 authored by Christophe Leroy's avatar Christophe Leroy Committed by Michael Ellerman
Browse files

powerpc: permanently include 8xx registers in reg.h



Most 8xx registers have specific names, so just include
reg_8xx.h all the time in reg.h in order to have them defined
even when CONFIG_PPC_8xx is not selected. This will avoid
the need for #ifdefs in C code.

Guard SPRN_ICTRL in an #ifdef CONFIG_PPC_8xx as this register
has same name but different meaning and different spr number as
another register in the mpc7450.

Signed-off-by: default avatarChristophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/dd82934ad91aab607d0eb7e626c14e6ac0d654eb.1567068137.git.christophe.leroy@c-s.fr
parent b0617434
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+1 −0
Original line number Diff line number Diff line
@@ -3,6 +3,7 @@
#define _ASM_POWERPC_KUP_8XX_H_

#include <asm/bug.h>
#include <asm/mmu.h>

#ifdef CONFIG_PPC_KUAP

+0 −2
Original line number Diff line number Diff line
@@ -25,9 +25,7 @@
#include <asm/reg_fsl_emb.h>
#endif

#ifdef CONFIG_PPC_8xx
#include <asm/reg_8xx.h>
#endif /* CONFIG_PPC_8xx */

#define MSR_SF_LG	63              /* Enable 64 bit mode */
#define MSR_ISF_LG	61              /* Interrupt 64b mode valid on 630 */
+2 −2
Original line number Diff line number Diff line
@@ -5,8 +5,6 @@
#ifndef _ASM_POWERPC_REG_8xx_H
#define _ASM_POWERPC_REG_8xx_H

#include <asm/mmu.h>

/* Cache control on the MPC8xx is provided through some additional
 * special purpose registers.
 */
@@ -38,7 +36,9 @@
#define SPRN_CMPF	153
#define SPRN_LCTRL1	156
#define SPRN_LCTRL2	157
#ifdef CONFIG_PPC_8xx
#define SPRN_ICTRL	158
#endif
#define SPRN_BAR	159

/* Commands.  Only the first few are available to the instruction cache.