Commit 4429e575 authored by Vivek Gautam's avatar Vivek Gautam Committed by Andy Gross
Browse files

arm64: dts: sdm845: Add node for arm,mmu-500 



Add device node for arm,mmu-500 available on sdm845.
This MMU-500 with single TCU and multiple TBU architecture
is shared among all the peripherals except gpu.

Signed-off-by: default avatarVivek Gautam <vivek.gautam@codeaurora.org>
Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: default avatarAndy Gross <andy.gross@linaro.org>
parent b454dbdb

arch/arm64/boot/dts/qcom/sdm845.dtsi

+72 −0
Original line number Diff line number Diff line
@@ -1590,6 +1590,78 @@ 
			cell-index = <0>;

		};



		apps_smmu: iommu@15000000 {

			compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";

			reg = <0x15000000 0x80000>;

			#iommu-cells = <2>;

			#global-interrupts = <1>;

			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;

		};



		apss_shared: mailbox@17990000 {

			compatible = "qcom,sdm845-apss-shared";

			reg = <0x17990000 0x1000>;

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