Commit 4411805b authored by Marc Kleine-Budde's avatar Marc Kleine-Budde Committed by Sascha Hauer
Browse files

imx serial: set RXD mux bit on i.MX27 and i.MX31 



RX in i.MX27 and i.MX31 UART lines does not work unless the
"RXD  Muxed Input Select" bit is set on i.MX27 and i.MX31 processors.

This patch sets the missing RXD mux bit in the UCR3 register.

Signed-off-by: default avatarMarc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: default avatarSascha Hauer <s.hauer@pengutronix.de>
parent c45e7d7b

drivers/serial/imx.c

+13 −2
Original line number Diff line number Diff line
@@ -127,8 +127,13 @@ 
#define  UCR3_RXDSEN	 (1<<6)  /* Receive status interrupt enable */

#define  UCR3_AIRINTEN   (1<<5)  /* Async IR wake interrupt enable */

#define  UCR3_AWAKEN	 (1<<4)  /* Async wake interrupt enable */

#define  UCR3_REF25 	 (1<<3)  /* Ref freq 25 MHz */

#define  UCR3_REF30 	 (1<<2)  /* Ref Freq 30 MHz */

#ifdef CONFIG_ARCH_IMX

#define  UCR3_REF25 	 (1<<3)  /* Ref freq 25 MHz, only on mx1 */

#define  UCR3_REF30 	 (1<<2)  /* Ref Freq 30 MHz, only on mx1 */

#endif

#if defined CONFIG_ARCH_MX2 || defined CONFIG_ARCH_MX3

#define  UCR3_RXDMUXSEL	 (1<<2)  /* RXD Muxed Input Select, on mx2/mx3 */

#endif

#define  UCR3_INVT  	 (1<<1)  /* Inverted Infrared transmission */

#define  UCR3_BPEN  	 (1<<0)  /* Preset registers enable */

#define  UCR4_CTSTL_32   (32<<10) /* CTS trigger level (32 chars) */
@@ -598,6 +603,12 @@ static int imx_startup(struct uart_port *port) 
	temp |= (UCR2_RXEN | UCR2_TXEN);

	writel(temp, sport->port.membase + UCR2);



#if defined CONFIG_ARCH_MX2 || defined CONFIG_ARCH_MX3

	temp = readl(sport->port.membase + UCR3);

	temp |= UCR3_RXDMUXSEL;

	writel(temp, sport->port.membase + UCR3);

#endif



	/*

	 * Enable modem status interrupts

	 */

CRA Git | Maintained and supported by SUSTech CRA and CCSE