clk: bcm2835: Add BCM2711_CLOCK_EMMC2 support (42de9ad4) · Commits · 戴 / test

drivers/clk/bcm/clk-bcm2835.c

+19 −1

Original line number	Diff line number	Diff line
		@@ -114,6 +114,8 @@
		#define CM_AVEODIV 0x1bc
		#define CM_EMMCCTL 0x1c0
		#define CM_EMMCDIV 0x1c4
		#define CM_EMMC2CTL 0x1d0
		#define CM_EMMC2DIV 0x1d4

		/* General bits for the CM_CTL regs /
		# define CM_ENABLE BIT(4)
		@@ -290,7 +292,8 @@
		#define BCM2835_MAX_FB_RATE 1750000000u

		#define SOC_BCM2835 BIT(0)
		#define SOC_ALL (SOC_BCM2835)
		#define SOC_BCM2711 BIT(1)
		#define SOC_ALL (SOC_BCM2835 \| SOC_BCM2711)

		/*
		* Names of clocks used within the driver that need to be replaced
		@@ -2003,6 +2006,16 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
		.frac_bits = 8,
		.tcnt_mux = 39),

		/* EMMC2 clock (only available for BCM2711) */
		[BCM2711_CLOCK_EMMC2] = REGISTER_PER_CLK(
		SOC_BCM2711,
		.name = "emmc2",
		.ctl_reg = CM_EMMC2CTL,
		.div_reg = CM_EMMC2DIV,
		.int_bits = 4,
		.frac_bits = 8,
		.tcnt_mux = 42),

		/* General purpose (GPIO) clocks */
		[BCM2835_CLOCK_GP0] = REGISTER_PER_CLK(
		SOC_ALL,
		@@ -2238,8 +2251,13 @@ static const struct cprman_plat_data cprman_bcm2835_plat_data = {
		.soc = SOC_BCM2835,
		};

		static const struct cprman_plat_data cprman_bcm2711_plat_data = {
		.soc = SOC_BCM2711,
		};

		static const struct of_device_id bcm2835_clk_of_match[] = {
		{ .compatible = "brcm,bcm2835-cprman", .data = &cprman_bcm2835_plat_data },
		{ .compatible = "brcm,bcm2711-cprman", .data = &cprman_bcm2711_plat_data },
		{}
		};
		MODULE_DEVICE_TABLE(of, bcm2835_clk_of_match);