Commit 429d939c authored Jan 17, 2020 by Yangbo Lu Committed by Ulf Hansson Jan 20, 2020

mmc: sdhci-of-esdhc: fix transfer mode register reading



The standard SD controller uses two 16-bit registers for
command sending.
0xC: Transfer Mode Register
0xE: Command Register

But the eSDHC controller uses one 32-bit register instead.
0xC: XFERTYPE

For Transfer Mode Register and Command Register writing,
the eSDHC driver will store Transfer Mode Register value in
a variable first. When Command Register writing happens,
driver will directly write a 32-bit value into XFERTYPE
register.

But for Transfer Mode Register reading, driver just returns
a actual value. This may cause issue for some read-modify-write
operations. We should make both reading and write on that variable
for Transfer Mode Register.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Link: https://lore.kernel.org/r/20200117063858.37296-1-yangbo.lu@nxp.com


Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>

parent 2fefc7c5

drivers/mmc/host/sdhci-of-esdhc.c

+3 −0

Original line number	Diff line number	Diff line
		@@ -173,6 +173,9 @@ static u16 esdhc_readw_fixup(struct sdhci_host *host,
		u16 ret;
		int shift = (spec_reg & 0x2) * 8;

		if (spec_reg == SDHCI_TRANSFER_MODE)
		return pltfm_host->xfer_mode_shadow;

		if (spec_reg == SDHCI_HOST_VERSION)
		ret = value & 0xffff;
		else

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