Commit 42724dd8 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'hisi-arm64-dt-for-4.20' of git://github.com/hisilicon/linux-hisi into next/dt 

ARM64: DT: Hisilicon SoC DT updates for 4.20

- Add missing clocks for Hi6220
- Switch to updated coresight bindings for Hi6220
- Add DT bindings and support for Hi3670 SoC and HiKey970 board

* tag 'hisi-arm64-dt-for-4.20' of git://github.com/hisilicon/linux-hisi

:
  arm64: dts: Add devicetree support for HiKey970 board
  dt-bindings: arm: hisilicon: Add binding for HiKey970 board
  arm64: dts: Add devicetree for Hisilicon Hi3670 SoC
  dt-bindings: arm: hisilicon: Add binding for Hi3670 SoC
  arm64: dts: hi6220: Update coresight bindings for hardware ports
  arm64: dts: hisilicon: Add missing clocks property for CPUs

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 45351fa3 5510ee99

Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt

+8 −0
Original line number Diff line number Diff line
@@ -8,6 +8,14 @@ HiKey960 Board 
Required root node properties:

	- compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660";



Hi3670 SoC

Required root node properties:

	- compatible = "hisilicon,hi3670";



HiKey970 Board

Required root node properties:

	- compatible = "hisilicon,hi3670-hikey970", "hisilicon,hi3670";



Hi3798cv200 SoC

Required root node properties:

	- compatible = "hisilicon,hi3798cv200";

arch/arm64/boot/dts/hisilicon/Makefile

+1 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0

dtb-$(CONFIG_ARCH_HISI) += hi3660-hikey960.dtb

dtb-$(CONFIG_ARCH_HISI) += hi3670-hikey970.dtb

dtb-$(CONFIG_ARCH_HISI) += hi3798cv200-poplar.dtb

dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb

dtb-$(CONFIG_ARCH_HISI) += hip05-d02.dtb

arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts

0 → 100644
+35 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/*

 * dts file for Hisilicon HiKey970 Development Board

 *

 * Copyright (C) 2016, Hisilicon Ltd.

 * Copyright (C) 2018, Linaro Ltd.

 *

 */



/dts-v1/;



#include "hi3670.dtsi"



/ {

	model = "HiKey970";

	compatible = "hisilicon,hi3670-hikey970", "hisilicon,hi3670";



	aliases {

		serial6 = &uart6;       /* console UART */

	};



	chosen {

		stdout-path = "serial6:115200n8";

	};



	memory@0 {

		device_type = "memory";

		/* expect bootloader to fill in this region */

		reg = <0x0 0x0 0x0 0x0>;

	};

};



&uart6 {

	status = "okay";

};

arch/arm64/boot/dts/hisilicon/hi3670.dtsi

0 → 100644
+162 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/*

 * dts file for Hisilicon Hi3670 SoC

 *

 * Copyright (C) 2016, Hisilicon Ltd.

 * Copyright (C) 2018, Linaro Ltd.

 */



#include <dt-bindings/interrupt-controller/arm-gic.h>



/ {

	compatible = "hisilicon,hi3670";

	interrupt-parent = <&gic>;

	#address-cells = <2>;

	#size-cells = <2>;



	psci {

		compatible = "arm,psci-0.2";

		method = "smc";

	};



	cpus {

		#address-cells = <2>;

		#size-cells = <0>;



		cpu-map {

			cluster0 {

				core0 {

					cpu = <&cpu0>;

				};

				core1 {

					cpu = <&cpu1>;

				};

				core2 {

					cpu = <&cpu2>;

				};

				core3 {

					cpu = <&cpu3>;

				};

			};

			cluster1 {

				core0 {

					cpu = <&cpu4>;

				};

				core1 {

					cpu = <&cpu5>;

				};

				core2 {

					cpu = <&cpu6>;

				};

				core3 {

					cpu = <&cpu7>;

				};

			};

		};



		cpu0: cpu@0 {

			compatible = "arm,cortex-a53", "arm,armv8";

			device_type = "cpu";

			reg = <0x0 0x0>;

			enable-method = "psci";

		};



		cpu1: cpu@1 {

			compatible = "arm,cortex-a53", "arm,armv8";

			device_type = "cpu";

			reg = <0x0 0x1>;

			enable-method = "psci";

		};



		cpu2: cpu@2 {

			compatible = "arm,cortex-a53", "arm,armv8";

			device_type = "cpu";

			reg = <0x0 0x2>;

			enable-method = "psci";

		};



		cpu3: cpu@3 {

			compatible = "arm,cortex-a53", "arm,armv8";

			device_type = "cpu";

			reg = <0x0 0x3>;

			enable-method = "psci";

		};



		cpu4: cpu@100 {

			compatible = "arm,cortex-a73", "arm,armv8";

			device_type = "cpu";

			reg = <0x0 0x100>;

			enable-method = "psci";

		};



		cpu5: cpu@101 {

			compatible = "arm,cortex-a73", "arm,armv8";

			device_type = "cpu";

			reg = <0x0 0x101>;

			enable-method = "psci";

		};



		cpu6: cpu@102 {

			compatible = "arm,cortex-a73", "arm,armv8";

			device_type = "cpu";

			reg = <0x0 0x102>;

			enable-method = "psci";

		};



		cpu7: cpu@103 {

			compatible = "arm,cortex-a73", "arm,armv8";

			device_type = "cpu";

			reg = <0x0 0x103>;

			enable-method = "psci";

		};

	};



	gic: interrupt-controller@e82b0000 {

		compatible = "arm,gic-400";

		reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */

		      <0x0 0xe82b2000 0 0x2000>, /* GICC */

		      <0x0 0xe82b4000 0 0x2000>, /* GICH */

		      <0x0 0xe82b6000 0 0x2000>; /* GICV */

		#interrupt-cells = <3>;

		#address-cells = <0>;

		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |

					 IRQ_TYPE_LEVEL_HIGH)>;

		interrupt-controller;

	};



	timer {

		compatible = "arm,armv8-timer";

		interrupt-parent = <&gic>;

		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) |

					  IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) |

					  IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) |

					  IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) |

					  IRQ_TYPE_LEVEL_LOW)>;

		clock-frequency = <1920000>;

	};



	soc {

		compatible = "simple-bus";

		#address-cells = <2>;

		#size-cells = <2>;

		ranges;



		uart6_clk: clk_19_2M {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <19200000>;

		};



		uart6: serial@fff32000 {

			compatible = "arm,pl011", "arm,primecell";

			reg = <0x0 0xfff32000 0x0 0x1000>;

			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&uart6_clk &uart6_clk>;

			clock-names = "uartclk", "apb_pclk";

			status = "disabled";

		};

	};

};

arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi

+86 −95
Original line number Diff line number Diff line
@@ -20,22 +20,18 @@ 
			clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;

			clock-names = "apb_pclk";



			ports {

				#address-cells = <1>;

				#size-cells = <0>;



				port@0 {

					reg = <0>;

			out-ports {

				port {

					soc_funnel_out: endpoint {

						remote-endpoint =

							<&etf_in>;

					};

				};

			};



				port@1 {

					reg = <0>;

			in-ports {

				port {

					soc_funnel_in: endpoint {

						slave-mode;

						remote-endpoint =

							<&acpu_funnel_out>;

					};
@@ -49,21 +45,17 @@ 
			clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;

			clock-names = "apb_pclk";



			ports {

				#address-cells = <1>;

				#size-cells = <0>;



				port@0 {

					reg = <0>;

			in-ports {

				port {

					etf_in: endpoint {

						slave-mode;

						remote-endpoint =

							<&soc_funnel_out>;

					};

				};

			};



				port@1 {

					reg = <0>;

			out-ports {

				port {

					etf_out: endpoint {

						remote-endpoint =

							<&replicator_in>;
@@ -77,20 +69,20 @@ 
			clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;

			clock-names = "apb_pclk";



			ports {

				#address-cells = <1>;

				#size-cells = <0>;



				port@0 {

					reg = <0>;

			in-ports {

				port {

					replicator_in: endpoint {

						slave-mode;

						remote-endpoint =

							<&etf_out>;

					};

				};

			};



				port@1 {

			out-ports {

				#address-cells = <1>;

				#size-cells = <0>;



				port@0 {

					reg = <0>;

					replicator_out0: endpoint {

						remote-endpoint =
@@ -98,7 +90,7 @@ 
					};

				};



				port@2 {

				port@1 {

					reg = <1>;

					replicator_out1: endpoint {

						remote-endpoint =
@@ -114,14 +106,9 @@ 
			clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;

			clock-names = "apb_pclk";



			ports {

				#address-cells = <1>;

				#size-cells = <0>;



				port@0 {

					reg = <0>;

			in-ports {

				port {

					etr_in: endpoint {

						slave-mode;

						remote-endpoint =

							<&replicator_out0>;

					};
@@ -135,14 +122,9 @@ 
			clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;

			clock-names = "apb_pclk";



			ports {

				#address-cells = <1>;

				#size-cells = <0>;



				port@0 {

					reg = <0>;

			in-ports {

				port {

					tpiu_in: endpoint {

						slave-mode;

						remote-endpoint =

							<&replicator_out1>;

					};
@@ -156,85 +138,78 @@ 
			clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;

			clock-names = "apb_pclk";



			ports {

				#address-cells = <1>;

				#size-cells = <0>;



				port@0 {

					reg = <0>;

			out-ports {

				port {

					acpu_funnel_out: endpoint {

						remote-endpoint =

							<&soc_funnel_in>;

					};

				};

			};



				port@1 {

			in-ports {

				#address-cells = <1>;

				#size-cells = <0>;



				port@0 {

					reg = <0>;

					acpu_funnel_in0: endpoint {

						slave-mode;

						remote-endpoint =

							<&etm0_out>;

					};

				};



				port@2 {

				port@1 {

					reg = <1>;

					acpu_funnel_in1: endpoint {

						slave-mode;

						remote-endpoint =

							<&etm1_out>;

					};

				};



				port@3 {

				port@2 {

					reg = <2>;

					acpu_funnel_in2: endpoint {

						slave-mode;

						remote-endpoint =

							<&etm2_out>;

					};

				};



				port@4 {

				port@3 {

					reg = <3>;

					acpu_funnel_in3: endpoint {

						slave-mode;

						remote-endpoint =

							<&etm3_out>;

					};

				};



				port@5 {

				port@4 {

					reg = <4>;

					acpu_funnel_in4: endpoint {

						slave-mode;

						remote-endpoint =

							<&etm4_out>;

					};

				};



				port@6 {

				port@5 {

					reg = <5>;

					acpu_funnel_in5: endpoint {

						slave-mode;

						remote-endpoint =

							<&etm5_out>;

					};

				};



				port@7 {

				port@6 {

					reg = <6>;

					acpu_funnel_in6: endpoint {

						slave-mode;

						remote-endpoint =

							<&etm6_out>;

					};

				};



				port@8 {

				port@7 {

					reg = <7>;

					acpu_funnel_in7: endpoint {

						slave-mode;

						remote-endpoint =

							<&etm7_out>;

					};
@@ -251,6 +226,7 @@ 


			cpu = <&cpu0>;



			out-ports {

				port {

					etm0_out: endpoint {

						remote-endpoint =
@@ -258,6 +234,7 @@ 
					};

				};

			};

		};



		etm@f659d000 {

			compatible = "arm,coresight-etm4x", "arm,primecell";
@@ -268,6 +245,7 @@ 


			cpu = <&cpu1>;



			out-ports {

				port {

					etm1_out: endpoint {

						remote-endpoint =
@@ -275,6 +253,7 @@ 
					};

				};

			};

		};



		etm@f659e000 {

			compatible = "arm,coresight-etm4x", "arm,primecell";
@@ -285,6 +264,7 @@ 


			cpu = <&cpu2>;



			out-ports {

				port {

					etm2_out: endpoint {

						remote-endpoint =
@@ -292,6 +272,7 @@ 
					};

				};

			};

		};



		etm@f659f000 {

			compatible = "arm,coresight-etm4x", "arm,primecell";
@@ -302,6 +283,7 @@ 


			cpu = <&cpu3>;



			out-ports {

				port {

					etm3_out: endpoint {

						remote-endpoint =
@@ -309,6 +291,7 @@ 
					};

				};

			};

		};



		etm@f65dc000 {

			compatible = "arm,coresight-etm4x", "arm,primecell";
@@ -319,6 +302,7 @@ 


			cpu = <&cpu4>;



			out-ports {

				port {

					etm4_out: endpoint {

						remote-endpoint =
@@ -326,6 +310,7 @@ 
					};

				};

			};

		};



		etm@f65dd000 {

			compatible = "arm,coresight-etm4x", "arm,primecell";
@@ -336,6 +321,7 @@ 


			cpu = <&cpu5>;



			out-ports {

				port {

					etm5_out: endpoint {

						remote-endpoint =
@@ -343,6 +329,7 @@ 
					};

				};

			};

		};



		etm@f65de000 {

			compatible = "arm,coresight-etm4x", "arm,primecell";
@@ -353,6 +340,7 @@ 


			cpu = <&cpu6>;



			out-ports {

				port {

					etm6_out: endpoint {

						remote-endpoint =
@@ -360,6 +348,7 @@ 
					};

				};

			};

		};



		etm@f65df000 {

			compatible = "arm,coresight-etm4x", "arm,primecell";
@@ -370,6 +359,7 @@ 


			cpu = <&cpu7>;



			out-ports {

				port {

					etm7_out: endpoint {

						remote-endpoint =
@@ -379,3 +369,4 @@ 
			};

		};

	};

};

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