Commit 426b3b8d authored by Stefan Assmann's avatar Stefan Assmann Committed by Ingo Molnar
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pci: add quirk to disable boot interrupt generation on intel 6300ESB 



Add a quirk to disable legacy boot interrupt generation on intel devices
that support disabling it.

This patch benefited from discussions with Alexander Graf, Torsten Duwe,
Ihno Krumreich, Daniel Gollub, Hannes Reinecke. The conclusions we drew
and the patch itself are the authors' responsibility alone.

Signed-off-by: default avatarStefan Assmann <sassmann@suse.de>
Signed-off-by: default avatarOlaf Dabrunz <od@suse.de>
Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
parent 9197979b

drivers/pci/quirks.c

+30 −0
Original line number Diff line number Diff line
@@ -1363,6 +1363,36 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm); 
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x260a, quirk_intel_pcie_pm);

DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x260b, quirk_intel_pcie_pm);



#ifdef CONFIG_X86_IO_APIC

/*

 * On some chipsets we can disable the generation of legacy INTx boot

 * interrupts.

 */



/*

 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no

 * 300641-004US, section 5.7.3.

 */

#define INTEL_6300_IOAPIC_ABAR		0x40

#define INTEL_6300_DISABLE_BOOT_IRQ	(1<<14)



static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)

{

	u16 pci_config_word;



	if (noioapicquirk)

		return;



	pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);

	pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;

	pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);



	printk(KERN_INFO "disabled boot interrupt on device 0x%04x:0x%04x\n",

		dev->vendor, dev->device);

}

DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ESB_10, 	quirk_disable_intel_boot_interrupt);

#endif /* CONFIG_X86_IO_APIC */



/*

 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size

 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.

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