Commit 4257f7e0 authored by Vidya Sagar's avatar Vidya Sagar Committed by Bjorn Helgaas
Browse files

PCI/ASPM: Save/restore L1SS Capability for suspend/resume 

Previously ASPM L1 Substates control registers (CTL1 and CTL2) weren't
saved and restored during suspend/resume leading to L1 Substates
configuration being lost post-resume.

Save the L1 Substates control registers so that the configuration is
retained post-resume.

Link: https://lore.kernel.org/r/20201024190442.871-1-vidyas@nvidia.com


Signed-off-by: default avatarVidya Sagar <vidyas@nvidia.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
parent f8394f23

drivers/pci/pci.c

+7 −0
Original line number Diff line number Diff line
@@ -1564,6 +1564,7 @@ int pci_save_state(struct pci_dev *dev) 
		return i;



	pci_save_ltr_state(dev);

	pci_save_aspm_l1ss_state(dev);

	pci_save_dpc_state(dev);

	pci_save_aer_state(dev);

	return pci_save_vc_state(dev);
@@ -1669,6 +1670,7 @@ void pci_restore_state(struct pci_dev *dev) 
	 * LTR itself (in the PCIe capability).

	 */

	pci_restore_ltr_state(dev);

	pci_restore_aspm_l1ss_state(dev);



	pci_restore_pcie_state(dev);

	pci_restore_pasid_state(dev);
@@ -3332,6 +3334,11 @@ void pci_allocate_cap_save_buffers(struct pci_dev *dev) 
	if (error)

		pci_err(dev, "unable to allocate suspend buffer for LTR\n");



	error = pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_L1SS,

					    2 * sizeof(u32));

	if (error)

		pci_err(dev, "unable to allocate suspend buffer for ASPM-L1SS\n");



	pci_allocate_vc_save_buffers(dev);

}

drivers/pci/pci.h

+4 −0
Original line number Diff line number Diff line
@@ -564,11 +564,15 @@ void pcie_aspm_init_link_state(struct pci_dev *pdev); 
void pcie_aspm_exit_link_state(struct pci_dev *pdev);

void pcie_aspm_pm_state_change(struct pci_dev *pdev);

void pcie_aspm_powersave_config_link(struct pci_dev *pdev);

void pci_save_aspm_l1ss_state(struct pci_dev *dev);

void pci_restore_aspm_l1ss_state(struct pci_dev *dev);

#else

static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { }

static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { }

static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev) { }

static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { }

static inline void pci_save_aspm_l1ss_state(struct pci_dev *dev) { }

static inline void pci_restore_aspm_l1ss_state(struct pci_dev *dev) { }

#endif



#ifdef CONFIG_PCIE_ECRC

drivers/pci/pcie/aspm.c

+44 −0
Original line number Diff line number Diff line
@@ -734,6 +734,50 @@ static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state) 
				PCI_L1SS_CTL1_L1SS_MASK, val);

}



void pci_save_aspm_l1ss_state(struct pci_dev *dev)

{

	int aspm_l1ss;

	struct pci_cap_saved_state *save_state;

	u32 *cap;



	if (!pci_is_pcie(dev))

		return;



	aspm_l1ss = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_L1SS);

	if (!aspm_l1ss)

		return;



	save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_L1SS);

	if (!save_state)

		return;



	cap = (u32 *)&save_state->cap.data[0];

	pci_read_config_dword(dev, aspm_l1ss + PCI_L1SS_CTL1, cap++);

	pci_read_config_dword(dev, aspm_l1ss + PCI_L1SS_CTL2, cap++);

}



void pci_restore_aspm_l1ss_state(struct pci_dev *dev)

{

	int aspm_l1ss;

	struct pci_cap_saved_state *save_state;

	u32 *cap;



	if (!pci_is_pcie(dev))

		return;



	aspm_l1ss = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_L1SS);

	if (!aspm_l1ss)

		return;



	save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_L1SS);

	if (!save_state)

		return;



	cap = (u32 *)&save_state->cap.data[0];

	pci_write_config_dword(dev, aspm_l1ss + PCI_L1SS_CTL1, *cap++);

	pci_write_config_dword(dev, aspm_l1ss + PCI_L1SS_CTL2, *cap++);

}



static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val)

{

	pcie_capability_clear_and_set_word(pdev, PCI_EXP_LNKCTL,

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