Commit 421ca868 authored Oct 23, 2019 by Alexey Budankov Committed by Ingo Molnar Oct 28, 2019

perf/x86/intel: Implement LBR callstack context synchronization



Implement intel_pmu_lbr_swap_task_ctx() method updating counters
of the events that requested LBR callstack data on a sample.

The counter can be zero for the case when task context belongs to
a thread that has just come from a block on a futex and the context
contains saved (lbr_stack_state == LBR_VALID) LBR register values.

For the values to be restored at LBR registers on the next thread's
switch-in event it swaps the counter value with the one that is
expected to be non zero at the previous equivalent task perf event
context.

Swap operation type ensures the previous task perf event context
stays consistent with the amount of events that requested LBR
callstack data on a sample.

Signed-off-by: Alexey Budankov <alexey.budankov@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Kan Liang <kan.liang@linux.intel.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Song Liu <songliubraving@fb.com>
Cc: Stephane Eranian <eranian@google.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Vince Weaver <vincent.weaver@maine.edu>
Link: https://lkml.kernel.org/r/261ac742-9022-c3f4-5885-1eae7415b091@linux.intel.com


Signed-off-by: Ingo Molnar <mingo@kernel.org>

parent a4439970

arch/x86/events/intel/lbr.c

+23 −0

Original line number	Diff line number	Diff line
		@@ -417,6 +417,29 @@ static void __intel_pmu_lbr_save(struct x86_perf_task_context *task_ctx)
		cpuc->last_log_id = ++task_ctx->log_id;
		}

		void intel_pmu_lbr_swap_task_ctx(struct perf_event_context *prev,
		struct perf_event_context *next)
		{
		struct x86_perf_task_context prev_ctx_data, next_ctx_data;

		swap(prev->task_ctx_data, next->task_ctx_data);

		/*
		* Architecture specific synchronization makes sense in
		* case both prev->task_ctx_data and next->task_ctx_data
		* pointers are allocated.
		*/

		prev_ctx_data = next->task_ctx_data;
		next_ctx_data = prev->task_ctx_data;

		if (!prev_ctx_data \|\| !next_ctx_data)
		return;

		swap(prev_ctx_data->lbr_callstack_users,
		next_ctx_data->lbr_callstack_users);
		}

		void intel_pmu_lbr_sched_task(struct perf_event_context *ctx, bool sched_in)
		{
		struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);

arch/x86/events/perf_event.h

+3 −0

Original line number	Diff line number	Diff line
		@@ -1024,6 +1024,9 @@ void intel_pmu_store_pebs_lbrs(struct pebs_lbr *lbr);

		void intel_ds_init(void);

		void intel_pmu_lbr_swap_task_ctx(struct perf_event_context *prev,
		struct perf_event_context *next);

		void intel_pmu_lbr_sched_task(struct perf_event_context *ctx, bool sched_in);

		u64 lbr_from_signext_quirk_wr(u64 val);

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