Commit 41fb666d authored by Wenhui Sheng's avatar Wenhui Sheng Committed by Alex Deucher
Browse files

drm/amd/powerplay: remove SRIOV check in SMU11 (v2) 



We don't need SRIOV check after we enable SMC msg filter in SMU11

v2: squash in unused variable fix, unused ids

Signed-off-by: default avatarWenhui Sheng <Wenhui.Sheng@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: default avatarKevin Wang <kevin1.wang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 4ea5081c

drivers/gpu/drm/amd/powerplay/amdgpu_smu.c

+72 −83
Original line number Diff line number Diff line
@@ -563,10 +563,8 @@ int smu_update_table(struct smu_context *smu, enum smu_table_id table_index, int 


bool is_support_sw_smu(struct amdgpu_device *adev)

{

	if (adev->asic_type >= CHIP_ARCTURUS) {

	      if (amdgpu_sriov_is_pp_one_vf(adev) || !amdgpu_sriov_vf(adev))

	if (adev->asic_type >= CHIP_ARCTURUS)

		return true;

	}



	return false;

}
@@ -1109,7 +1107,6 @@ static int smu_smc_table_hw_init(struct smu_context *smu, 
		return ret;



	/* smu_dump_pptable(smu); */

	if (!amdgpu_sriov_vf(adev)) {

	/*

	 * Copy pptable bo in the vram to smc with SMU MSGs such as

	 * SetDriverDramAddr and TransferTableDram2Smu.
@@ -1131,14 +1128,10 @@ static int smu_smc_table_hw_init(struct smu_context *smu, 
		return ret;



	if (adev->asic_type == CHIP_NAVI10) {

			if ((adev->pdev->device == 0x731f && (adev->pdev->revision == 0xc2 ||

		if (adev->pdev->device == 0x731f && (adev->pdev->revision == 0xc2 ||

						     adev->pdev->revision == 0xc3 ||

						     adev->pdev->revision == 0xca ||

							      adev->pdev->revision == 0xcb)) ||

			    (adev->pdev->device == 0x66af && (adev->pdev->revision == 0xf3 ||

							      adev->pdev->revision == 0xf4 ||

							      adev->pdev->revision == 0xf5 ||

							      adev->pdev->revision == 0xf6))) {

						     adev->pdev->revision == 0xcb)) {

			ret = smu_disable_umc_cdr_12gbps_workaround(smu);

			if (ret) {

				pr_err("Workaround failed to disable UMC CDR feature on 12Gbps SKU!\n");
@@ -1161,7 +1154,7 @@ static int smu_smc_table_hw_init(struct smu_context *smu, 
			return ret;

		}

	}

	}



	if (adev->asic_type != CHIP_ARCTURUS) {

		ret = smu_notify_display_change(smu);

		if (ret)
@@ -1214,9 +1207,8 @@ static int smu_smc_table_hw_init(struct smu_context *smu, 
	/*

	 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools.

	 */

	if (!amdgpu_sriov_vf(adev)) {

	ret = smu_set_tool_table_location(smu);

	}



	if (!smu_is_dpm_running(smu))

		pr_info("dpm has been disabled\n");
@@ -1376,9 +1368,6 @@ failed: 


static int smu_stop_dpms(struct smu_context *smu)

{

	if (amdgpu_sriov_vf(smu->adev))

		return 0;



	return smu_system_features_control(smu, false);

}
@@ -1405,6 +1394,7 @@ static int smu_hw_fini(void *handle) 


	if (!amdgpu_sriov_vf(adev)) {

		smu_i2c_eeprom_fini(smu, &adev->pm.smu_i2c);

	}



	ret = smu_stop_thermal_control(smu);

	if (ret) {
@@ -1432,7 +1422,6 @@ static int smu_hw_fini(void *handle) 
			return ret;

		}

	}

	}



	kfree(table_context->driver_pptable);

	table_context->driver_pptable = NULL;
@@ -1548,11 +1537,11 @@ static int smu_suspend(void *handle) 


	if (!amdgpu_sriov_vf(adev)) {

		smu_i2c_eeprom_fini(smu, &adev->pm.smu_i2c);

	}



	ret = smu_disable_dpm(smu);

	if (ret)

		return ret;

	}



	smu->watermarks_bitmap &= ~(WATERMARKS_LOADED);

drivers/gpu/drm/amd/powerplay/arcturus_ppt.c

+3 −4
Original line number Diff line number Diff line
@@ -1335,7 +1335,6 @@ static int arcturus_get_power_limit(struct smu_context *smu, 
static int arcturus_get_power_profile_mode(struct smu_context *smu,

					   char *buf)

{

	struct amdgpu_device *adev = smu->adev;

	DpmActivityMonitorCoeffInt_t activity_monitor;

	static const char *profile_name[] = {

					"BOOTUP_DEFAULT",
@@ -1369,7 +1368,7 @@ static int arcturus_get_power_profile_mode(struct smu_context *smu, 
	if (result)

		return result;



	if (smu_version >= 0x360d00 && !amdgpu_sriov_vf(adev))

	if (smu_version >= 0x360d00)

		size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",

			title[0], title[1], title[2], title[3], title[4], title[5],

			title[6], title[7], title[8], title[9], title[10]);
@@ -1386,7 +1385,7 @@ static int arcturus_get_power_profile_mode(struct smu_context *smu, 
		if (workload_type < 0)

			continue;



		if (smu_version >= 0x360d00 && !amdgpu_sriov_vf(adev)) {

		if (smu_version >= 0x360d00) {

			result = smu_update_table(smu,

						  SMU_TABLE_ACTIVITY_MONITOR_COEFF,

						  workload_type,
@@ -1401,7 +1400,7 @@ static int arcturus_get_power_profile_mode(struct smu_context *smu, 
		size += sprintf(buf + size, "%2d %14s%s\n",

			i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");



		if (smu_version >= 0x360d00 && !amdgpu_sriov_vf(adev)) {

		if (smu_version >= 0x360d00) {

			size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",

				" ",

				0,

drivers/gpu/drm/amd/powerplay/navi10_ppt.c

+1 −5
Original line number Diff line number Diff line
@@ -1818,8 +1818,7 @@ static int navi10_get_power_limit(struct smu_context *smu, 
	int power_src;



	if (!smu->power_limit) {

		if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT) &&

			!amdgpu_sriov_vf(smu->adev)) {

		if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {

			power_src = smu_power_get_index(smu, SMU_POWER_SOURCE_AC);

			if (power_src < 0)

				return -EINVAL;
@@ -1962,9 +1961,6 @@ static int navi10_set_default_od_settings(struct smu_context *smu, bool initiali 
	OverDriveTable_t *od_table, *boot_od_table;

	int ret = 0;



	if (amdgpu_sriov_vf(smu->adev))

		return 0;



	ret = smu_v11_0_set_default_od_settings(smu, initialize, sizeof(OverDriveTable_t));

	if (ret)

		return ret;

drivers/gpu/drm/amd/powerplay/smu_v11_0.c

+0 −24
Original line number Diff line number Diff line
@@ -768,9 +768,6 @@ int smu_v11_0_set_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk) 
{

	int ret;



	if (amdgpu_sriov_vf(smu->adev))

		return 0;



	ret = smu_send_smc_msg_with_param(smu,

					  SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL);

	if (ret)
@@ -814,9 +811,6 @@ int smu_v11_0_set_tool_table_location(struct smu_context *smu) 
	int ret = 0;

	struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];



	if (amdgpu_sriov_vf(smu->adev))

		return 0;



	if (tool_table->mc_address) {

		ret = smu_send_smc_msg_with_param(smu,

				SMU_MSG_SetToolsDramAddrHigh,
@@ -836,9 +830,6 @@ int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count) 
{

	int ret = 0;



	if (amdgpu_sriov_vf(smu->adev))

		return 0;



	if (!smu->pm_enabled)

		return ret;
@@ -853,9 +844,6 @@ int smu_v11_0_set_allowed_mask(struct smu_context *smu) 
	int ret = 0;

	uint32_t feature_mask[2];



	if (amdgpu_sriov_vf(smu->adev))

		return 0;



	mutex_lock(&feature->mutex);

	if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64)

		goto failed;
@@ -884,9 +872,6 @@ int smu_v11_0_get_enabled_mask(struct smu_context *smu, 
	struct smu_feature *feature = &smu->smu_feature;

	int ret = 0;



	if (amdgpu_sriov_vf(smu->adev) && !amdgpu_sriov_is_pp_one_vf(smu->adev))

		return 0;



	if (!feature_mask || num < 2)

		return -EINVAL;
@@ -942,9 +927,6 @@ int smu_v11_0_notify_display_change(struct smu_context *smu) 
{

	int ret = 0;



	if (amdgpu_sriov_vf(smu->adev))

		return 0;



	if (!smu->pm_enabled)

		return ret;
@@ -1107,9 +1089,6 @@ int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n) 
	int ret = 0;

	uint32_t max_power_limit;



	if (amdgpu_sriov_vf(smu->adev))

		return 0;



	max_power_limit = smu_v11_0_get_max_power_limit(smu);



	if (n > max_power_limit) {
@@ -1866,9 +1845,6 @@ int smu_v11_0_override_pcie_parameters(struct smu_context *smu) 
	uint32_t pcie_gen = 0, pcie_width = 0;

	int ret;



	if (amdgpu_sriov_vf(smu->adev))

		return 0;



	if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)

		pcie_gen = 3;

	else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)

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