Commit 41f03a6d authored by Dmytro Laktyushkin's avatar Dmytro Laktyushkin Committed by Alex Deucher
Browse files

drm/amd/display: fix dcn20 global sync dml param extraction 



Currently the paremeters are extracted as if dml is calculating
using pipes as we pass them in. in reality, dml internally merges
pipes into planes if pipe split is detected.

This change adds reverse logic to dcn20_calculate_dlg_params so
that the global sync parameters can be correctly extracted for
all the pipes when pipe split is enabled.

Signed-off-by: default avatarDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: default avatarCharlene Liu <Charlene.Liu@amd.com>
Acked-by: default avatarLeo Li <sunpeng.li@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 2c95e35f

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c

+131 −98
Original line number Diff line number Diff line
@@ -2540,7 +2540,8 @@ void dcn20_calculate_dlg_params( 
		int pipe_cnt,

		int vlevel)

{

	int i, pipe_idx;

	int i, j, pipe_idx, pipe_idx_unsplit;

	bool visited[MAX_PIPES] = { 0 };



	/* Writeback MCIF_WB arbitration parameters */

	dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt);
@@ -2556,23 +2557,55 @@ void dcn20_calculate_dlg_params( 
							!= dm_dram_clock_change_unsupported;

	context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;



	/*

	 * An artifact of dml pipe split/odm is that pipes get merged back together for

	 * calculation. Therefore we need to only extract for first pipe in ascending index order

	 * and copy into the other split half.

	 */

	for (i = 0, pipe_idx = 0, pipe_idx_unsplit = 0; i < dc->res_pool->pipe_count; i++) {

		if (!context->res_ctx.pipe_ctx[i].stream)

			continue;



		if (!visited[pipe_idx]) {

			display_pipe_source_params_st *src = &pipes[pipe_idx_unsplit].pipe.src;

			display_pipe_dest_params_st *dst = &pipes[pipe_idx_unsplit].pipe.dest;



			dst->vstartup_start = context->bw_ctx.dml.vba.VStartup[pipe_idx_unsplit];

			dst->vupdate_offset = context->bw_ctx.dml.vba.VUpdateOffsetPix[pipe_idx_unsplit];

			dst->vupdate_width = context->bw_ctx.dml.vba.VUpdateWidthPix[pipe_idx_unsplit];

			dst->vready_offset = context->bw_ctx.dml.vba.VReadyOffsetPix[pipe_idx_unsplit];

			/*

			 * j iterates inside pipes array, unlike i which iterates inside

			 * pipe_ctx array

			 */

			if (src->is_hsplit)

				for (j = pipe_idx + 1; j < pipe_cnt; j++) {

					display_pipe_source_params_st *src_j = &pipes[j].pipe.src;

					display_pipe_dest_params_st *dst_j = &pipes[j].pipe.dest;



					if (src_j->is_hsplit && !visited[j]

							&& src->hsplit_grp == src_j->hsplit_grp) {

						dst_j->vstartup_start = context->bw_ctx.dml.vba.VStartup[pipe_idx_unsplit];

						dst_j->vupdate_offset = context->bw_ctx.dml.vba.VUpdateOffsetPix[pipe_idx_unsplit];

						dst_j->vupdate_width = context->bw_ctx.dml.vba.VUpdateWidthPix[pipe_idx_unsplit];

						dst_j->vready_offset = context->bw_ctx.dml.vba.VReadyOffsetPix[pipe_idx_unsplit];

						visited[j] = true;

					}

				}

			visited[pipe_idx] = true;

			pipe_idx_unsplit++;

		}

		pipe_idx++;

	}



	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {

		if (!context->res_ctx.pipe_ctx[i].stream)

			continue;

		pipes[pipe_idx].pipe.dest.vstartup_start = context->bw_ctx.dml.vba.VStartup[pipe_idx];

		pipes[pipe_idx].pipe.dest.vupdate_offset = context->bw_ctx.dml.vba.VUpdateOffsetPix[pipe_idx];

		pipes[pipe_idx].pipe.dest.vupdate_width = context->bw_ctx.dml.vba.VUpdateWidthPix[pipe_idx];

		pipes[pipe_idx].pipe.dest.vready_offset = context->bw_ctx.dml.vba.VReadyOffsetPix[pipe_idx];

		if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)

			context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;

		context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz =

						pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;

#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT

		context->res_ctx.pipe_ctx[i].stream_res.dscclk_khz =

				context->bw_ctx.dml.vba.DSCCLK_calculated[pipe_idx] * 1000;

#endif

		ASSERT(visited[pipe_idx]);

		context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;

		pipe_idx++;

	}

drivers/gpu/drm/amd/display/dc/inc/core_types.h

+0 −1
Original line number Diff line number Diff line
@@ -234,7 +234,6 @@ struct stream_resource { 
	struct output_pixel_processor *opp;

#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT

	struct display_stream_compressor *dsc;

	int dscclk_khz;

#endif

	struct timing_generator *tg;

	struct stream_encoder *stream_enc;

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