Commit 41e69778 authored by Rob Clark's avatar Rob Clark
Browse files

drm/msm: DT support for 8960/8064 (v3) 



Now that we (almost) have enough dependencies in place (MMCC, RPM, etc),
add necessary DT support so that we can use drm/msm on upstream kernel.

v2: update for review comments
v3: rebase on component helper changes

Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
parent 8f67da33

Documentation/devicetree/bindings/drm/msm/gpu.txt

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+52 −0
Original line number Diff line number Diff line 
Qualcomm adreno/snapdragon GPU



Required properties:

- compatible: "qcom,adreno-3xx"

- reg: Physical base address and length of the controller's registers.

- interrupts: The interrupt signal from the gpu.

- clocks: device clocks

  See ../clocks/clock-bindings.txt for details.

- clock-names: the following clocks are required:

  * "core_clk"

  * "iface_clk"

  * "mem_iface_clk"

- qcom,chipid: gpu chip-id.  Note this may become optional for future

  devices if we can reliably read the chipid from hw

- qcom,gpu-pwrlevels: list of operating points

  - compatible: "qcom,gpu-pwrlevels"

  - for each qcom,gpu-pwrlevel:

    - qcom,gpu-freq: requested gpu clock speed

    - NOTE: downstream android driver defines additional parameters to

      configure memory bandwidth scaling per OPP.



Example:



/ {

	...



	gpu: qcom,kgsl-3d0@4300000 {

		compatible = "qcom,adreno-3xx";

		reg = <0x04300000 0x20000>;

		reg-names = "kgsl_3d0_reg_memory";

		interrupts = <GIC_SPI 80 0>;

		interrupt-names = "kgsl_3d0_irq";

		clock-names =

		    "core_clk",

		    "iface_clk",

		    "mem_iface_clk";

		clocks =

		    <&mmcc GFX3D_CLK>,

		    <&mmcc GFX3D_AHB_CLK>,

		    <&mmcc MMSS_IMEM_AHB_CLK>;

		qcom,chipid = <0x03020100>;

		qcom,gpu-pwrlevels {

			compatible = "qcom,gpu-pwrlevels";

			qcom,gpu-pwrlevel@0 {

				qcom,gpu-freq = <450000000>;

			};

			qcom,gpu-pwrlevel@1 {

				qcom,gpu-freq = <27000000>;

			};

		};

	};

};

Documentation/devicetree/bindings/drm/msm/hdmi.txt

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+46 −0
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Qualcomm adreno/snapdragon hdmi output



Required properties:

- compatible: one of the following

   * "qcom,hdmi-tx-8660"

   * "qcom,hdmi-tx-8960"

- reg: Physical base address and length of the controller's registers

- reg-names: "core_physical"

- interrupts: The interrupt signal from the hdmi block.

- clocks: device clocks

  See ../clocks/clock-bindings.txt for details.

- qcom,hdmi-tx-ddc-clk-gpio: ddc clk pin

- qcom,hdmi-tx-ddc-data-gpio: ddc data pin

- qcom,hdmi-tx-hpd-gpio: hpd pin

- core-vdda-supply: phandle to supply regulator

- hdmi-mux-supply: phandle to mux regulator



Optional properties:

- qcom,hdmi-tx-mux-en-gpio: hdmi mux enable pin

- qcom,hdmi-tx-mux-sel-gpio: hdmi mux select pin



Example:



/ {

	...



	hdmi: qcom,hdmi-tx-8960@4a00000 {

		compatible = "qcom,hdmi-tx-8960";

		reg-names = "core_physical";

		reg = <0x04a00000 0x1000>;

		interrupts = <GIC_SPI 79 0>;

		clock-names =

		    "core_clk",

		    "master_iface_clk",

		    "slave_iface_clk";

		clocks =

		    <&mmcc HDMI_APP_CLK>,

		    <&mmcc HDMI_M_AHB_CLK>,

		    <&mmcc HDMI_S_AHB_CLK>;

		qcom,hdmi-tx-ddc-clk = <&msmgpio 70 GPIO_ACTIVE_HIGH>;

		qcom,hdmi-tx-ddc-data = <&msmgpio 71 GPIO_ACTIVE_HIGH>;

		qcom,hdmi-tx-hpd = <&msmgpio 72 GPIO_ACTIVE_HIGH>;

		core-vdda-supply = <&pm8921_hdmi_mvs>;

		hdmi-mux-supply = <&ext_3p3v>;

	};

};

Documentation/devicetree/bindings/drm/msm/mdp.txt

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+48 −0
Original line number Diff line number Diff line 
Qualcomm adreno/snapdragon display controller



Required properties:

- compatible:

  * "qcom,mdp" - mdp4

- reg: Physical base address and length of the controller's registers.

- interrupts: The interrupt signal from the display controller.

- connectors: array of phandles for output device(s)

- clocks: device clocks

  See ../clocks/clock-bindings.txt for details.

- clock-names: the following clocks are required:

  * "core_clk"

  * "iface_clk"

  * "lut_clk"

  * "src_clk"

  * "hdmi_clk"

  * "mpd_clk"



Optional properties:

- gpus: phandle for gpu device



Example:



/ {

	...



	mdp: qcom,mdp@5100000 {

		compatible = "qcom,mdp";

		reg = <0x05100000 0xf0000>;

		interrupts = <GIC_SPI 75 0>;

		connectors = <&hdmi>;

		gpus = <&gpu>;

		clock-names =

		    "core_clk",

		    "iface_clk",

		    "lut_clk",

		    "src_clk",

		    "hdmi_clk",

		    "mdp_clk";

		clocks =

		    <&mmcc MDP_SRC>,

		    <&mmcc MDP_AHB_CLK>,

		    <&mmcc MDP_LUT_CLK>,

		    <&mmcc TV_SRC>,

		    <&mmcc HDMI_TV_CLK>,

		    <&mmcc MDP_TV_CLK>;

	};

};

drivers/gpu/drm/msm/adreno/a3xx_gpu.c

+2 −0
Original line number Diff line number Diff line
@@ -680,6 +680,8 @@ static int a3xx_remove(struct platform_device *pdev) 
}



static const struct of_device_id dt_match[] = {

	{ .compatible = "qcom,adreno-3xx" },

	/* for backwards compat w/ downstream kgsl DT files: */

	{ .compatible = "qcom,kgsl-3d0" },

	{}

};

drivers/gpu/drm/msm/hdmi/hdmi.c

+45 −23
Original line number Diff line number Diff line
@@ -123,7 +123,8 @@ struct hdmi *hdmi_init(struct drm_device *dev, struct drm_encoder *encoder) 
	for (i = 0; i < config->hpd_reg_cnt; i++) {

		struct regulator *reg;



		reg = devm_regulator_get(&pdev->dev, config->hpd_reg_names[i]);

		reg = devm_regulator_get_exclusive(&pdev->dev,

				config->hpd_reg_names[i]);

		if (IS_ERR(reg)) {

			ret = PTR_ERR(reg);

			dev_err(dev->dev, "failed to get hpd regulator: %s (%d)\n",
@@ -138,7 +139,8 @@ struct hdmi *hdmi_init(struct drm_device *dev, struct drm_encoder *encoder) 
	for (i = 0; i < config->pwr_reg_cnt; i++) {

		struct regulator *reg;



		reg = devm_regulator_get(&pdev->dev, config->pwr_reg_names[i]);

		reg = devm_regulator_get_exclusive(&pdev->dev,

				config->pwr_reg_names[i]);

		if (IS_ERR(reg)) {

			ret = PTR_ERR(reg);

			dev_err(dev->dev, "failed to get pwr regulator: %s (%d)\n",
@@ -265,23 +267,26 @@ static int hdmi_bind(struct device *dev, struct device *master, void *data) 
	int get_gpio(const char *name)

	{

		int gpio = of_get_named_gpio(of_node, name, 0);

		if (gpio < 0) {

			char name2[32];

			snprintf(name2, sizeof(name2), "%s-gpio", name);

			gpio = of_get_named_gpio(of_node, name2, 0);

			if (gpio < 0) {

				dev_err(dev, "failed to get gpio: %s (%d)\n",

						name, gpio);

				gpio = -1;

			}

		}

		return gpio;

	}



	/* TODO actually use DT.. */

	if (of_device_is_compatible(of_node, "qcom,hdmi-tx-8074")) {

		static const char *hpd_reg_names[] = {"hpd-gdsc", "hpd-5v"};

		static const char *pwr_reg_names[] = {"core-vdda", "core-vcc"};

		static const char *hpd_clk_names[] = {"iface_clk", "core_clk", "mdp_core_clk"};

		static unsigned long hpd_clk_freq[] = {0, 19200000, 0};

		static const char *pwr_clk_names[] = {"extp_clk", "alt_iface_clk"};



		config.phy_init      = hdmi_phy_8x74_init;

	config.mmio_name     = "core_physical";

		config.hpd_reg_names = hpd_reg_names;

		config.hpd_reg_cnt   = ARRAY_SIZE(hpd_reg_names);

		config.pwr_reg_names = pwr_reg_names;
@@ -291,12 +296,27 @@ static int hdmi_bind(struct device *dev, struct device *master, void *data) 
		config.hpd_clk_cnt   = ARRAY_SIZE(hpd_clk_names);

		config.pwr_clk_names = pwr_clk_names;

		config.pwr_clk_cnt   = ARRAY_SIZE(pwr_clk_names);

		config.shared_irq    = true;

	} else if (of_device_is_compatible(of_node, "qcom,hdmi-tx-8960")) {

		static const char *hpd_clk_names[] = {"core_clk", "master_iface_clk", "slave_iface_clk"};

		static const char *hpd_reg_names[] = {"core-vdda", "hdmi-mux"};

		config.phy_init      = hdmi_phy_8960_init;

		config.hpd_reg_names = hpd_reg_names;

		config.hpd_reg_cnt   = ARRAY_SIZE(hpd_reg_names);

		config.hpd_clk_names = hpd_clk_names;

		config.hpd_clk_cnt   = ARRAY_SIZE(hpd_clk_names);

	} else if (of_device_is_compatible(of_node, "qcom,hdmi-tx-8660")) {

		config.phy_init      = hdmi_phy_8x60_init;

	} else {

		dev_err(dev, "unknown phy: %s\n", of_node->name);

	}



	config.mmio_name     = "core_physical";

	config.ddc_clk_gpio  = get_gpio("qcom,hdmi-tx-ddc-clk");

	config.ddc_data_gpio = get_gpio("qcom,hdmi-tx-ddc-data");

	config.hpd_gpio      = get_gpio("qcom,hdmi-tx-hpd");

	config.mux_en_gpio   = get_gpio("qcom,hdmi-tx-mux-en");

	config.mux_sel_gpio  = get_gpio("qcom,hdmi-tx-mux-sel");

	config.shared_irq    = true;



#else

	static const char *hpd_clk_names[] = {
@@ -373,7 +393,9 @@ static int hdmi_dev_remove(struct platform_device *pdev) 
}



static const struct of_device_id dt_match[] = {

	{ .compatible = "qcom,hdmi-tx" },

	{ .compatible = "qcom,hdmi-tx-8074" },

	{ .compatible = "qcom,hdmi-tx-8960" },

	{ .compatible = "qcom,hdmi-tx-8660" },

	{}

};

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