Commit 41bbeadc authored by Vanessa Maegima's avatar Vanessa Maegima Committed by Shawn Guo
Browse files

ARM: dts: imx7d-pico-pi: Separate into cpu and baseboard dts 



Separate the old imx7d-pico into cpu (imx7d-pico.dtsi) and baseboard
(imx7d-pico-pi.dts) dts so the same cpu dtsi can be used in different
baseboards variants.

Signed-off-by: default avatarVanessa Maegima <vanessa.maegima@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent c5ecd77e

arch/arm/boot/dts/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -521,7 +521,7 @@ dtb-$(CONFIG_SOC_IMX7D) += \ 
	imx7d-cl-som-imx7.dtb \

	imx7d-colibri-eval-v3.dtb \

	imx7d-nitrogen7.dtb \

	imx7d-pico.dtb \

	imx7d-pico-pi.dtb \

	imx7d-sbc-imx7.dtb \

	imx7d-sdb.dtb \

	imx7d-sdb-sht11.dtb \

arch/arm/boot/dts/imx7d-pico-pi.dts

0 → 100644
+181 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2017 NXP

 *

 * This file is dual-licensed: you can use it either under the terms

 * of the GPL or the X11 license, at your option. Note that this dual

 * licensing only applies to this file, and not this project as a

 * whole.

 *

 *  a) This file is free software; you can redistribute it and/or

 *     modify it under the terms of the GNU General Public License as

 *     published by the Free Software Foundation; either version 2 of the

 *     License, or (at your option) any later version.

 *

 *     This file is distributed in the hope that it will be useful,

 *     but WITHOUT ANY WARRANTY; without even the implied warranty of

 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 *     GNU General Public License for more details.

 *

 * Or, alternatively,

 *

 *  b) Permission is hereby granted, free of charge, to any person

 *     obtaining a copy of this software and associated documentation

 *     files (the "Software"), to deal in the Software without

 *     restriction, including without limitation the rights to use,

 *     copy, modify, merge, publish, distribute, sublicense, and/or

 *     sell copies of the Software, and to permit persons to whom the

 *     Software is furnished to do so, subject to the following

 *     conditions:

 *

 *     The above copyright notice and this permission notice shall be

 *     included in all copies or substantial portions of the Software.

 *

 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,

 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES

 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND

 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT

 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,

 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING

 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 *     OTHER DEALINGS IN THE SOFTWARE.

 */



#include "imx7d-pico.dtsi"



/ {

	sound {

		compatible = "simple-audio-card";

		simple-audio-card,name = "imx7-sgtl5000";

		simple-audio-card,format = "i2s";

		simple-audio-card,bitclock-master = <&dailink_master>;

		simple-audio-card,frame-master = <&dailink_master>;

		simple-audio-card,cpu {

			sound-dai = <&sai1>;

		};



		dailink_master: simple-audio-card,codec {

			sound-dai = <&codec>;

			clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;

		};

	};

};



&fec1 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_enet1>;

	assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,

			  <&clks IMX7D_ENET1_TIME_ROOT_CLK>;

	assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;

	assigned-clock-rates = <0>, <100000000>;

	phy-mode = "rgmii";

	phy-handle = <&ethphy0>;

	fsl,magic-packet;

	status = "okay";



	mdio {

		#address-cells = <1>;

		#size-cells = <0>;



		ethphy0: ethernet-phy@1 {

			compatible = "ethernet-phy-ieee802.3-c22";

			reg = <1>;

			status = "okay";

		};

	};

};



&i2c1 {

	clock-frequency = <100000>;

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_i2c1>;

	status = "okay";



	codec: sgtl5000@a {

		#sound-dai-cells = <0>;

		reg = <0x0a>;

		compatible = "fsl,sgtl5000";

		clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;

		VDDA-supply = <&reg_2p5v>;

		VDDIO-supply = <&reg_vref_1v8>;

	};

};





&sai1 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_sai1>;

	assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,

			  <&clks IMX7D_SAI1_ROOT_CLK>;

	assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;

	assigned-clock-rates = <0>, <24576000>;

	status = "okay";

};



&uart5 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_uart5>;

	assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>;

	assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;

	status = "okay";

};



&usbotg1 {

	vbus-supply = <&reg_usb_otg1_vbus>;

	status = "okay";

};



&usbotg2 {

	vbus-supply = <&reg_usb_otg2_vbus>;

	dr_mode = "host";

	status = "okay";

};



&iomuxc {

	pinctrl_enet1: enet1grp {

		fsl,pins = <

			MX7D_PAD_SD2_CD_B__ENET1_MDIO			0x3

			MX7D_PAD_SD2_WP__ENET1_MDC			0x3

			MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC	0x1

			MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0	0x1

			MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1	0x1

			MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2	0x1

			MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3	0x1

			MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL	0x1

			MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC	0x1

			MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0	0x1

			MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1	0x1

			MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2	0x1

			MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3	0x1

			MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL	0x1

		>;

	};



	pinctrl_i2c1: i2c1grp {

		fsl,pins = <

			MX7D_PAD_UART1_TX_DATA__I2C1_SDA	0x4000007f

			MX7D_PAD_UART1_RX_DATA__I2C1_SCL	0x4000007f

		>;

	};



	pinctrl_sai1: sai1grp {

		fsl,pins = <

			MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK	0x1f

			MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC	0x1f

			MX7D_PAD_ENET1_COL__SAI1_TX_DATA0	0x30

			MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0	0x1f

		>;

	};



	pinctrl_uart5: uart5grp {

		fsl,pins = <

			MX7D_PAD_I2C4_SDA__UART5_DCE_TX		0x79

			MX7D_PAD_I2C4_SCL__UART5_DCE_RX		0x79

		>;

	};



	pinctrl_usbotg1_pwr: usbotg_pwr {

		fsl,pins = <

			MX7D_PAD_UART3_TX_DATA__GPIO4_IO5	0x14

		>;

	};

};

arch/arm/boot/dts/imx7d-pico.dts→arch/arm/boot/dts/imx7d-pico.dtsi

+0 −133
Original line number Diff line number Diff line
@@ -100,62 +100,6 @@ 
		regulator-min-microvolt = <1800000>;

		regulator-max-microvolt = <1800000>;

	};



	sound {

		compatible = "simple-audio-card";

		simple-audio-card,name = "imx7-sgtl5000";

		simple-audio-card,format = "i2s";

		simple-audio-card,bitclock-master = <&dailink_master>;

		simple-audio-card,frame-master = <&dailink_master>;

		simple-audio-card,cpu {

			sound-dai = <&sai1>;

		};



		dailink_master: simple-audio-card,codec {

			sound-dai = <&codec>;

			clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;

		};

	};

};



&fec1 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_enet1>;

	assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,

			  <&clks IMX7D_ENET1_TIME_ROOT_CLK>;

	assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;

	assigned-clock-rates = <0>, <100000000>;

	phy-mode = "rgmii";

	phy-handle = <&ethphy0>;

	fsl,magic-packet;

	status = "okay";



	mdio {

		#address-cells = <1>;

		#size-cells = <0>;



		ethphy0: ethernet-phy@1 {

			compatible = "ethernet-phy-ieee802.3-c22";

			reg = <1>;

			status = "okay";

		};

	};

};



&i2c1 {

	clock-frequency = <100000>;

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_i2c1>;

	status = "okay";



	codec: sgtl5000@a {

		#sound-dai-cells = <0>;

		reg = <0x0a>;

		compatible = "fsl,sgtl5000";

		clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;

		VDDA-supply = <&reg_2p5v>;

		VDDIO-supply = <&reg_vref_1v8>;

	};

};



&i2c4 {
@@ -253,35 +197,6 @@ 
	};

};



&sai1 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_sai1>;

	assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,

			  <&clks IMX7D_SAI1_ROOT_CLK>;

	assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;

	assigned-clock-rates = <0>, <24576000>;

	status = "okay";

};



&uart5 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_uart5>;

	assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>;

	assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;

	status = "okay";

};



&usbotg1 {

	vbus-supply = <&reg_usb_otg1_vbus>;

	status = "okay";

};



&usbotg2 {

	vbus-supply = <&reg_usb_otg2_vbus>;

	dr_mode = "host";

	status = "okay";

};



&usdhc2 { /* Wifi SDIO */

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_usdhc2>;
@@ -315,32 +230,6 @@ 
};



&iomuxc {

	pinctrl_enet1: enet1grp {

		fsl,pins = <

			MX7D_PAD_SD2_CD_B__ENET1_MDIO			0x3

			MX7D_PAD_SD2_WP__ENET1_MDC			0x3

			MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC	0x1

			MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0	0x1

			MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1	0x1

			MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2	0x1

			MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3	0x1

			MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL	0x1

			MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC	0x1

			MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0	0x1

			MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1	0x1

			MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2	0x1

			MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3	0x1

			MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL	0x1

		>;

	};



	pinctrl_i2c1: i2c1grp {

		fsl,pins = <

			MX7D_PAD_UART1_TX_DATA__I2C1_SDA	0x4000007f

			MX7D_PAD_UART1_RX_DATA__I2C1_SCL	0x4000007f

		>;

	};



	pinctrl_i2c4: i2c4grp {

		fsl,pins = <

			MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA		0x4000007f
@@ -354,28 +243,6 @@ 
		>;

	};



	pinctrl_sai1: sai1grp {

		fsl,pins = <

			MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK	0x1f

			MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC	0x1f

			MX7D_PAD_ENET1_COL__SAI1_TX_DATA0	0x30

			MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0	0x1f

		>;

	};



	pinctrl_uart5: uart5grp {

		fsl,pins = <

			MX7D_PAD_I2C4_SDA__UART5_DCE_TX		0x79

			MX7D_PAD_I2C4_SCL__UART5_DCE_RX		0x79

		>;

	};



	pinctrl_usbotg1_pwr: usbotg_pwr {

		fsl,pins = <

			MX7D_PAD_UART3_TX_DATA__GPIO4_IO5	0x14

		>;

	};



	pinctrl_usdhc2: usdhc2grp {

		fsl,pins = <

			MX7D_PAD_SD2_CMD__SD2_CMD		0x59

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