Commit 417f3d08 authored Feb 08, 2019 by Russell King Committed by David S. Miller Feb 08, 2019

net: marvell: mvpp2: read correct pause bits



When reading the pause bits in mac_link_state, mvpp2 was reporting
the state of the "active pause" bits, which are set when the MAC is
in pause mode.  This is not what phylink wants - we want the
negotiated pause state.  Fix the definition so we read the correct
bits.

Tested-by: Sven Auhagen <sven.auhagen@voleatech.de>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: David S. Miller <davem@davemloft.net>

parent d14e078f

drivers/net/ethernet/marvell/mvpp2/mvpp2.h

+2 −2

Original line number	Diff line number	Diff line
		@@ -402,8 +402,8 @@
		#define MVPP2_GMAC_STATUS0_GMII_SPEED BIT(1)
		#define MVPP2_GMAC_STATUS0_MII_SPEED BIT(2)
		#define MVPP2_GMAC_STATUS0_FULL_DUPLEX BIT(3)
		#define MVPP2_GMAC_STATUS0_RX_PAUSE BIT(6)
		#define MVPP2_GMAC_STATUS0_TX_PAUSE BIT(7)
		#define MVPP2_GMAC_STATUS0_RX_PAUSE BIT(4)
		#define MVPP2_GMAC_STATUS0_TX_PAUSE BIT(5)
		#define MVPP2_GMAC_STATUS0_AN_COMPLETE BIT(11)
		#define MVPP2_GMAC_PORT_FIFO_CFG_1_REG 0x1c
		#define MVPP2_GMAC_TX_FIFO_MIN_TH_OFFS 6

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