drm/i915: Handle all MCR ranges (415d1269) · Commits · 戴 / test

The bspec documents multiple MCR ranges; make sure they're all captured by the driver. Bspec: 13991, 52079 Fixes: ("drm/i915: Extend non readable mcr range") Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Signed-off-by:

Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200311162300.1838847-2-matthew.d.roper@intel.com Reviewed-by:

Mika Kuoppala <mika.kuoppala@linux.intel.com>

drivers/gpu/drm/i915/gt/intel_workarounds.c

+22 −3

Original line number	Diff line number	Diff line
		@@ -1648,14 +1648,33 @@ err_obj:
		return ERR_PTR(err);
		}

		static const struct {
		u32 start;
		u32 end;
		} mcr_ranges_gen8[] = {
		{ .start = 0x5500, .end = 0x55ff },
		{ .start = 0x7000, .end = 0x7fff },
		{ .start = 0x9400, .end = 0x97ff },
		{ .start = 0xb000, .end = 0xb3ff },
		{ .start = 0xe000, .end = 0xe7ff },
		{},
		};

		static bool mcr_range(struct drm_i915_private *i915, u32 offset)
		{
		int i;

		if (INTEL_GEN(i915) < 8)
		return false;

		/*
		* Registers in this range are affected by the MCR selector
		* Registers in these ranges are affected by the MCR selector
		* which only controls CPU initiated MMIO. Routing does not
		* work for CS access so we cannot verify them on this path.
		*/
		if (INTEL_GEN(i915) >= 8 && (offset >= 0xb000 && offset <= 0xb4ff))
		for (i = 0; mcr_ranges_gen8[i].start; i++)
		if (offset >= mcr_ranges_gen8[i].start &&
		offset <= mcr_ranges_gen8[i].end)
		return true;

		return false;

Admin message