Commit 414147d9 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'pci-v5.2-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci 

Pull PCI updates from Bjorn Helgaas:
 "Enumeration changes:

   - Add _HPX Type 3 settings support, which gives firmware more
     influence over device configuration (Alexandru Gagniuc)

   - Support fixed bus numbers from bridge Enhanced Allocation
     capabilities (Subbaraya Sundeep)

   - Add "external-facing" DT property to identify cases where we
     require IOMMU protection against untrusted devices (Jean-Philippe
     Brucker)

   - Enable PCIe services for host controller drivers that use managed
     host bridge alloc (Jean-Philippe Brucker)

   - Log PCIe port service messages with pci_dev, not the pcie_device
     (Frederick Lawler)

   - Convert pciehp from pciehp_debug module parameter to generic
     dynamic debug (Frederick Lawler)

  Peer-to-peer DMA:

   - Add whitelist of Root Complexes that support peer-to-peer DMA
     between Root Ports (Christian König)

  Native controller drivers:

   - Add PCI host bridge DMA ranges for bridges that can't DMA
     everywhere, e.g., iProc (Srinath Mannam)

   - Add Amazon Annapurna Labs PCIe host controller driver (Jonathan
     Chocron)

   - Fix Tegra MSI target allocation so DMA doesn't generate unwanted
     MSIs (Vidya Sagar)

   - Fix of_node reference leaks (Wen Yang)

   - Fix Hyper-V module unload & device removal issues (Dexuan Cui)

   - Cleanup R-Car driver (Marek Vasut)

   - Cleanup Keystone driver (Kishon Vijay Abraham I)

   - Cleanup i.MX6 driver (Andrey Smirnov)

  Significant bug fixes:

   - Reset Lenovo ThinkPad P50 GPU so nouveau works after reboot (Lyude
     Paul)

   - Fix Switchtec firmware update performance issue (Wesley Sheng)

   - Work around Pericom switch link retraining erratum (Stefan Mätje)"

* tag 'pci-v5.2-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (141 commits)
  MAINTAINERS: Add Karthikeyan Mitran and Hou Zhiqiang for Mobiveil PCI
  PCI: pciehp: Remove pointless MY_NAME definition
  PCI: pciehp: Remove pointless PCIE_MODULE_NAME definition
  PCI: pciehp: Remove unused dbg/err/info/warn() wrappers
  PCI: pciehp: Log messages with pci_dev, not pcie_device
  PCI: pciehp: Replace pciehp_debug module param with dyndbg
  PCI: pciehp: Remove pciehp_debug uses
  PCI/AER: Log messages with pci_dev, not pcie_device
  PCI/DPC: Log messages with pci_dev, not pcie_device
  PCI/PME: Replace dev_printk(KERN_DEBUG) with dev_info()
  PCI/AER: Replace dev_printk(KERN_DEBUG) with dev_info()
  PCI: Replace dev_printk(KERN_DEBUG) with dev_info(), etc
  PCI: Replace printk(KERN_INFO) with pr_info(), etc
  PCI: Use dev_printk() when possible
  PCI: Cleanup setup-bus.c comments and whitespace
  PCI: imx6: Allow asynchronous probing
  PCI: dwc: Save root bus for driver remove hooks
  PCI: dwc: Use devm_pci_alloc_host_bridge() to simplify code
  PCI: dwc: Free MSI in dw_pcie_host_init() error path
  PCI: dwc: Free MSI IRQ page in dw_pcie_free_msi()
  ...
parents 318222a3 c7a1c2bb

Documentation/devicetree/bindings/pci/designware-pcie.txt

+5 −2
Original line number Diff line number Diff line
@@ -4,8 +4,11 @@ Required properties: 
- compatible:

	"snps,dw-pcie" for RC mode;

	"snps,dw-pcie-ep" for EP mode;

- reg: Should contain the configuration address space.

- reg-names: Must be "config" for the PCIe configuration space.

- reg: For designware cores version < 4.80 contains the configuration

       address space. For designware core version >= 4.80, contains

       the configuration and ATU address space

- reg-names: Must be "config" for the PCIe configuration space and "atu" for

	     the ATU address space.

    (The old way of getting the configuration address space from "ranges"

    is deprecated and should be avoided.)

- num-lanes: number of lanes to use

Documentation/devicetree/bindings/pci/pci-keystone.txt

+55 −3
Original line number Diff line number Diff line
@@ -11,16 +11,24 @@ described here as well as properties that are not applicable. 


Required Properties:-



compatibility: "ti,keystone-pcie"

reg:	index 1 is the base address and length of DW application registers.

	index 2 is the base address and length of PCI device ID register.

compatibility: Should be "ti,keystone-pcie" for RC on Keystone2 SoC

	       Should be "ti,am654-pcie-rc" for RC on AM654x SoC

reg: Three register ranges as listed in the reg-names property

reg-names: "dbics" for the DesignWare PCIe registers, "app" for the

	   TI specific application registers, "config" for the

	   configuration space address



pcie_msi_intc : Interrupt controller device node for MSI IRQ chip

	interrupt-cells: should be set to 1

	interrupts: GIC interrupt lines connected to PCI MSI interrupt lines

	(required if the compatible is "ti,keystone-pcie")

msi-map: As specified in Documentation/devicetree/bindings/pci/pci-msi.txt

	 (required if the compatible is "ti,am654-pcie-rc".



ti,syscon-pcie-id : phandle to the device control module required to set device

		    id and vendor id.

ti,syscon-pcie-mode : phandle to the device control module required to configure

		      PCI in either RC mode or EP mode.



 Example:

	pcie_msi_intc: msi-interrupt-controller {
@@ -61,3 +69,47 @@ Optional properties:- 
DesignWare DT Properties not applicable for Keystone PCI



1. pcie_bus clock-names not used.  Instead, a phandle to phys is used.



AM654 PCIe Endpoint

===================



Required Properties:-



compatibility: Should be "ti,am654-pcie-ep" for EP on AM654x SoC

reg: Four register ranges as listed in the reg-names property

reg-names: "dbics" for the DesignWare PCIe registers, "app" for the

	   TI specific application registers, "atu" for the

	   Address Translation Unit configuration registers and

	   "addr_space" used to map remote RC address space

num-ib-windows: As specified in

		Documentation/devicetree/bindings/pci/designware-pcie.txt

num-ob-windows: As specified in

		Documentation/devicetree/bindings/pci/designware-pcie.txt

num-lanes: As specified in

	   Documentation/devicetree/bindings/pci/designware-pcie.txt

power-domains: As documented by the generic PM domain bindings in

	       Documentation/devicetree/bindings/power/power_domain.txt.

ti,syscon-pcie-mode: phandle to the device control module required to configure

		      PCI in either RC mode or EP mode.



Optional properties:-



phys: list of PHY specifiers (used by generic PHY framework)

phy-names: must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the

               number of lanes as specified in *num-lanes* property.

("phys" and "phy-names" DT bindings are specified in

Documentation/devicetree/bindings/phy/phy-bindings.txt)

interrupts: platform interrupt for error interrupts.



pcie-ep {

	compatible = "ti,am654-pcie-ep";

	reg =  <0x5500000 0x1000>, <0x5501000 0x1000>,

	       <0x10000000 0x8000000>, <0x5506000 0x1000>;

	reg-names = "app", "dbics", "addr_space", "atu";

	power-domains = <&k3_pds 120>;

	ti,syscon-pcie-mode = <&pcie0_mode>;

	num-lanes = <1>;

	num-ib-windows = <16>;

	num-ob-windows = <16>;

	interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;

};

Documentation/devicetree/bindings/pci/pci.txt

+50 −0
Original line number Diff line number Diff line
@@ -24,3 +24,53 @@ driver implementation may support the following properties: 
   unsupported link speed, for instance, trying to do training for

   unsupported link speed, etc.  Must be '4' for gen4, '3' for gen3, '2'

   for gen2, and '1' for gen1. Any other values are invalid.



PCI-PCI Bridge properties

-------------------------



PCIe root ports and switch ports may be described explicitly in the device

tree, as children of the host bridge node. Even though those devices are

discoverable by probing, it might be necessary to describe properties that

aren't provided by standard PCIe capabilities.



Required properties:



- reg:

   Identifies the PCI-PCI bridge. As defined in the IEEE Std 1275-1994

   document, it is a five-cell address encoded as (phys.hi phys.mid

   phys.lo size.hi size.lo). phys.hi should contain the device's BDF as

   0b00000000 bbbbbbbb dddddfff 00000000. The other cells should be zero.



   The bus number is defined by firmware, through the standard bridge

   configuration mechanism. If this port is a switch port, then firmware

   allocates the bus number and writes it into the Secondary Bus Number

   register of the bridge directly above this port. Otherwise, the bus

   number of a root port is the first number in the bus-range property,

   defaulting to zero.



   If firmware leaves the ARI Forwarding Enable bit set in the bridge

   above this port, then phys.hi contains the 8-bit function number as

   0b00000000 bbbbbbbb ffffffff 00000000. Note that the PCIe specification

   recommends that firmware only leaves ARI enabled when it knows that the

   OS is ARI-aware.



Optional properties:



- external-facing:

   When present, the port is external-facing. All bridges and endpoints

   downstream of this port are external to the machine. The OS can, for

   example, use this information to identify devices that cannot be

   trusted with relaxed DMA protection, as users could easily attach

   malicious devices to this port.



Example:



pcie@10000000 {

	compatible = "pci-host-ecam-generic";

	...

	pcie@0008 {

		/* Root port 00:01.0 is external-facing */

		reg = <0x00000800 0 0 0 0>;

		external-facing;

	};

};

MAINTAINERS

+8 −1
Original line number Diff line number Diff line
@@ -12026,7 +12026,8 @@ F: include/linux/switchtec.h 
F:	drivers/ntb/hw/mscc/



PCI DRIVER FOR MOBIVEIL PCIE IP

M:	Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>

M:	Karthikeyan Mitran <m.karthikeyan@mobiveil.co.in>

M:	Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

L:	linux-pci@vger.kernel.org

S:	Supported

F:	Documentation/devicetree/bindings/pci/mobiveil-pcie.txt
@@ -12160,6 +12161,12 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/lpieralisi/pci.git/ 
S:	Supported

F:	drivers/pci/controller/



PCIE DRIVER FOR ANNAPURNA LABS

M:	Jonathan Chocron <jonnyc@amazon.com>

L:	linux-pci@vger.kernel.org

S:	Maintained

F:	drivers/pci/controller/dwc/pcie-al.c



PCIE DRIVER FOR AMLOGIC MESON

M:	Yue Wang <yue.wang@Amlogic.com>

L:	linux-pci@vger.kernel.org

arch/arm64/boot/dts/mediatek/mt2712e.dtsi

+0 −2
Original line number Diff line number Diff line
@@ -819,7 +819,6 @@ 
			#size-cells = <2>;

			#interrupt-cells = <1>;

			ranges;

			num-lanes = <1>;

			interrupt-map-mask = <0 0 0 7>;

			interrupt-map = <0 0 0 1 &pcie_intc0 0>,

					<0 0 0 2 &pcie_intc0 1>,
@@ -840,7 +839,6 @@ 
			#size-cells = <2>;

			#interrupt-cells = <1>;

			ranges;

			num-lanes = <1>;

			interrupt-map-mask = <0 0 0 7>;

			interrupt-map = <0 0 0 1 &pcie_intc1 0>,

					<0 0 0 2 &pcie_intc1 1>,

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