drm/i915/tgl: Add DC3CO counter in i915_dmc_info (41286861) · Commits · 戴 / test

Adding DC3CO counter in i915_dmc_info debugfs will be useful for DC3CO validation. DMC firmware uses DMC_DEBUG3 register as DC3CO counter register on TGL, as per B.Specs DMC_DEBUG3 is general purpose register. v1: comment modification for DMC_DBUG3. using GEN >= 12 check instead of IS_TIGERLAKE() to print DMC_DEBUG3 counter value. Cc: Jani Nikula <jani.nikula@intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Animesh Manna <animesh.manna@intel.com> Reviewed-by:

Imre Deak <imre.deak@intel.com> Signed-off-by:

Anshuman Gupta <anshuman.gupta@intel.com> Signed-off-by:

Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191003081738.22101-7-anshuman.gupta@intel.com

drivers/gpu/drm/i915/i915_debugfs.c

+7 −0

Original line number	Diff line number	Diff line
		@@ -2405,6 +2405,13 @@ static int i915_dmc_info(struct seq_file m, void unused)
		if (INTEL_GEN(dev_priv) >= 12) {
		dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
		dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
		/*
		* NOTE: DMC_DEBUG3 is a general purpose reg.
		* According to B.Specs:49196 DMC f/w reuses DC5/6 counter
		* reg for DC3CO debugging and validation,
		* but TGL DMC f/w is using DMC_DEBUG3 reg for DC3CO counter.
		*/
		seq_printf(m, "DC3CO count: %d\n", I915_READ(DMC_DEBUG3));
		} else {
		dc5_reg = IS_BROXTON(dev_priv) ? BXT_CSR_DC3_DC5_COUNT :
		SKL_CSR_DC3_DC5_COUNT;

drivers/gpu/drm/i915/i915_reg.h

+2 −0

Original line number	Diff line number	Diff line
		@@ -7268,6 +7268,8 @@ enum {
		#define TGL_DMC_DEBUG_DC5_COUNT _MMIO(0x101084)
		#define TGL_DMC_DEBUG_DC6_COUNT _MMIO(0x101088)

		#define DMC_DEBUG3 _MMIO(0x101090)

		/* interrupts */
		#define DE_MASTER_IRQ_CONTROL (1 << 31)
		#define DE_SPRITEB_FLIP_DONE (1 << 29)

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