drm/i915: Fix IVB GT2 WaDisableDopClockGating and WaDisablePSDDualDispatchEnable (412236c2) · Commits · 戴 / test

IVB GT2 has two registers for these things, and both must be written. To add a bit more confusion both Bspec and the W/A database state that WaDisablePSDDualDispatchEnable is only needed for IVB GT1, but the W/A database also says to write even the second GT2 only register. So I don't really know what the right thing here is. Note that Bspec disagrees with the w/a database here, but Ville confirmed (by asking Chris) that on gt1 the 2nd reg doesn't exist. Signed-off-by:

Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:

Rodrigo Vivi <rodrigo.vivi@gmail.com> [danvet: Add note as requested by Rodrigo.] Signed-off-by:

Daniel Vetter <daniel.vetter@ffwll.ch>

drivers/gpu/drm/i915/intel_pm.c

+10 −3

Original line number	Diff line number	Diff line
		@@ -4825,9 +4825,13 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
		if (IS_IVB_GT1(dev))
		I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
		_MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
		else
		else {
		/* must write both registers */
		I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
		_MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
		I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
		_MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
		}

		/* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
		I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
		@@ -4841,10 +4845,13 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
		if (IS_IVB_GT1(dev))
		I915_WRITE(GEN7_ROW_CHICKEN2,
		_MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
		else
		else {
		/* must write both registers */
		I915_WRITE(GEN7_ROW_CHICKEN2,
		_MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
		I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
		_MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));

		}

		/* WaForceL3Serialization:ivb */
		I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &

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